Scribd
Upload
13 views3 pages

Arithmetic Woloop

This document contains code for an arithmetic logic unit (ALU) module and test bench. The ALU module takes in two 8-bit inputs (a and b), a 4-bit command, and an enable signal and outputs a 16-bit result. The module uses a case statement to perform different operations based on the command, including addition, increment, subtraction, etc. The test bench initializes values, sets the enable signal, inputs sample values to a and b, sets a command, adds a delay, and monitors the output.

Uploaded by

12 EC ATUL KUMAR SRIVASTAVA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
13 views3 pages

Arithmetic Woloop

This document contains code for an arithmetic logic unit (ALU) module and test bench. The ALU module takes in two 8-bit inputs (a and b), a 4-bit command, and an enable signal and outputs a 16-bit result. The module uses a case statement to perform different operations based on the command, including addition, increment, subtraction, etc. The test bench initializes values, sets the enable signal, inputs sample values to a and b, sets a command, adds a delay, and monitors the output.

Uploaded by

12 EC ATUL KUMAR SRIVASTAVA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

//RTL For ALU

module alu_wo_loop(input [7:0]a,b,input [3:0]command_in,input oe,output


[15:0]d_out);

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.


INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF

reg [15:0]out;
always@(command_in)
begin
case(command_in)
ADD: out=a+b;
INC: out=a+1;
SUB: out=a-b;
DEC: out=a-1;
MUL: out=a*b;
DIV: out=a/b;
SHL: out=a<<b;
SHR: out=a>>b;
AND: out=a&b;
OR: out=a|b;
INV: out=~a;
NAND:out=~(a&b);
NOR:out=~(a|b);
XOR:out=a^b;
XNOR:out=~(a^b);
BUF:out=a;

default: out=16'h0000;
endcase
end

assign d_out = (oe) ? out : 16'hzzzz;


endmodule
//Test bench for ALU
module alu_wo_loop_tb();
reg [7:0]a,b;
reg [3:0]command;
reg enable;
wire [15:0]out;

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.


INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF

reg [4*8:1]string_cmd;

alu_wo_loop dut(a,b,command,enable,out);

task initialize;
begin
{a,b}=16'h0000;
end
endtask

task en_oe(input i);


begin
enable=i;
end
endtask

task inputs(input [7:0]j,k);


begin
a=j;b=k;
end
endtask

task cmd(input [3:0]l);


begin
command=l;
end
endtask

task delay();
begin
#10;
end
endtask
always@(command)
begin
case (command)
ADD : string_cmd = "ADD";
INC : string_cmd = "INC";
SUB : string_cmd = "SUB";
DEC : string_cmd = "DEC";
MUL : string_cmd = "MUL";
DIV : string_cmd = "DIV";
SHL : string_cmd = "SHL";
SHR : string_cmd = "SHR";
INV : string_cmd = "INV";
AND : string_cmd = "AND";
OR : string_cmd = "OR";
NAND : string_cmd = "NAND";
NOR : string_cmd = "NOR";
XOR : string_cmd = "XOR";
XNOR : string_cmd = "XNOR";
BUF : string_cmd= "BUF";
endcase
end
initial
begin
initialize;
en_oe(1);
inputs(8'd25,8'd17);
cmd(ADD);
delay ;
$finish;
end
initial
$monitor("Input oe=%d, a=%d, b=%d, command=%s, Output
out=%d",enable,a,b,string_cmd,out);
endmodule

You might also like