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Experiment 2

The document describes designing a 32-bit ALU using Verilog. It includes writing code for the ALU using case statements and if statements, performing functional verification with a test bench, and synthesizing the design while setting area and timing constraints. It also compares the synthesis results of modeling the ALU using if and case statements.

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15 views3 pages

Experiment 2

The document describes designing a 32-bit ALU using Verilog. It includes writing code for the ALU using case statements and if statements, performing functional verification with a test bench, and synthesizing the design while setting area and timing constraints. It also compares the synthesis results of modeling the ALU using if and case statements.

Uploaded by

salilahegde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 2: Write verilog code for 32-bit ALU supporting four logical and four

arithmetic operations, use case statement and if statement for ALU behavioral modeling. a.
Perform functional verification using test bench b. Synthesize the design targeting suitable
library by setting area and timing constraints c. For various constrains set, tabulate the area,
power and delay for the synthesized netlist d. Identify the critical path and set the
constraints to obtain optimum gate level netlist with suitable constraints Compare the
synthesis results of ALU modeled using IF and CASE statements.
//Design block using case

module ALU_32bit(a,b,opcode,enable,y);

input [31:0] a,b; // declare input [31:0] a,b for 32 bit ALU

input [3:0] opcode; input enable;

output [63:0] y; // declare as output [63:0] y for 32 bit alu

reg [63:0] y; //declare as reg [63:0] y;

always@(a,b,enable,opcode)

begin

if(enable==1'b1)

begin

case (opcode)

4'b0001 :y= a+ b;

4'b0010 :y= a-b;

4'b0011 :y= a*b;

4'b0100 :y= a/ b;

4'b0101 :y= a& b;

4'b0110 :y= a|b;

4'b0111 : y = ~(a & b);

4'b1000 :y= a^ b;

default: y=32'd0; // y=32’d0;

endcase
end

else

begin

y=32'd0; //y=32’d0;

end

end

endmodule

//design block using if

module ALU_32bit(a,b,opcode,enable,y);

input [31:0] a,b; // declare input [31:0] a,b for 32 bit ALU

input [3:0] opcode; input enable;

output [63:0] y; // declare as output [63:0] y for 32 bit alu

reg [63:0] y; //declare as reg [63:0] y;

always@(a,b,enable,opcode)

begin

if(enable==1'b1)

begin

if (opcode == 4’b0000) y= a+b;

else if( opcode == 4'b0001) y = a-b;


else if( opcode == 4'b0010) y = a*b;
else if( opcode == 4'b0011) y = a/b;
else if( opcode == 4'b0100) y = a&b;
else if( opcode == 4'b0101) y = a|b;
else if( opcode == 4'b0110) y = ~(a&b);
else if( opcode == 4'b0111) y = a^b;
else y=32’d0;
end
end
endmodule

//Stimulus block

module testADC;

reg [31:0] a,b ; reg [3:0] opcode;


reg enable; wire [63:0] y;

ALU_32bit AA (.a(a),.b(b),opcode(opcode),.enable(enable),.y(y));

initial

begin

a=32’b10110111 0111 0111 10100101 01111000;

b=32’b10100101 0111100011001010; enable=0; opcode=4’d0;

#10 enable =1;

#10 opcode=4’d1; // you may give in binary as opcode=4’b0001;

#10 opcode =4’d2;

#10 opcode=4’d3;

#10 opcode =4’d4;

#10 opcode=4’d5;

#10 opcode =4’d6;

#10 opcode=4’d7;

#10 opcode =4’d8;

#10 opcode=4’d0;

#10; opcode =4’b1001; // try giving opcode 4’b 0x01, 00z0 etc

end

endmodule

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