IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO.

11, NOVEMBER 2022 4233

High SFDR Current-Steering DAC With

Splitting-and-Binary Segmented Architecture and
Dynamic-Element-Matching Technique
Xingyuan Tong , Member, IEEE, and Dong Liu

Abstract—This brief presents a current-steering digital-to-

analog converter (DAC) with “4-bit splitting + 8-bit binary”
segmented topology. The proposed splitting decoding method can
optimize the differential nonlinearity and output glitches of the
DAC with a more simplified circuit scale than unary decoding.
With a data-transmission topology, the splitting decoder has a
low latency and accommodates fast synchronization control of
current source switches. Moreover, the dynamic element match-
ing (DEM) technique is used to suppress the harmonic distortion
caused by the splitting current source mismatch. The DAC is
designed using 0.18-µm CMOS technology and occupies an area
of 452.82 µm × 491.76 µm. With a 1.8 V analog supply and a
1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s.
Fig. 1. Structure of the proposed current steering DAC.
The spurious-free dynamic range of the DAC improves from
63.18 dB to 73.30 dB using DEM technique for an output signal
of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.
Index Terms—Digital-to-analog converter, splitting decoder, reduce glitches but extra switches and signals increase power
data transmission, spurious-free dynamic range, mismatch. consumption and circuit scale [7]–[9].
The dynamic element matching (DEM) technique can
be used to randomize the selection of current sources,
I. I NTRODUCTION reducing the effect of current source mismatch on DAC
URRENT-STEERING digital-to-analog converters performance [10]–[12]. In [12], the DEM technique was
C (DACs) have been widely used in applications requiring
an accuracy over 10 bits and sampling rates of up to hundreds
adopted for the currents corresponding to the thermometer-
coded most significant bits (MSBs), for suppressing the effect
of millions of samples per second (MS/s) [1]–[2]. They of the current source mismatch on the SFDR. However, a
consist of an array of matched current sources that are usually DEM decoder with higher complexity can usually cause larger
binary- or unary-weighted [3]. Glitches usually occur in the latency, limiting the update rate of the DAC. Moreover, the
output signal at the major code transition of the binary- traditional thermometer decoder in a unary-weighted or unary-
weighted current-steering DAC, while it is significantly lower binary segmented current-steering DAC is often constructed
in thermometer-coded DAC [4]. However, with an increase using traditional NAND and NOR gates. Its latency increases
in resolution of the thermometer-coded DAC, the circuit considerably with the number of decoding bits, which can
scale for thermometer decoding and the complexity of the cause imperfect synchronization of the control signals of
wiring layout of a current source array increase significantly, switches and deteriorate the SFDR of the DAC.
and the systematic mismatch caused by the interconnection Herein, a 12-bit current steering DAC with a splitting-and-
parasitic effects of the current source array will also affect binary segmented architecture is proposed. The four MSBs
the spurious-free dynamic range (SFDR) [5]. On the other are converted into splitting codes and steer a splitting cur-
hand, the current source mismatch can cause considerable rent array [13]. The DEM technique is adopted for splitting
differential nonlinearity (DNL), and also leads to harmonic currents to suppress the SFDR deterioration caused by the
distortions that relates to the input data, which in return mismatch of splitting current sources. Superior to the tradi-
results in SFDR deterioration [6]. A quad-switching can tional binary-weighted approach, the splitting approach can
optimize the DNL and glitches with a reduced circuit scale
Manuscript received 31 May 2022; accepted 29 June 2022. Date of pub- compared with the unary decoding method. The proposed
lication 4 July 2022; date of current version 28 October 2022. This work splitting decoder with data-transmission topology achieves a
was supported in part by the National Natural Science Foundation of China
under Grant 61674122 and Grant 62104193. This brief was recommended by short delay and accommodates fast synchronization of the con-
Associate Editor Q. Liu. (Corresponding author: Xingyuan Tong.) trol signals of current source switches, improves the SFDR of
The authors are with the School of Electronics Engineering, Xi’an the DAC.
University of Posts and Telecommunications, Xi’an 710121, China (e-mail: The remainder of this brief is organized as follows.
tongxingyuan@xupt.edu.cn).
Color versions of one or more figures in this article are available at
Section II presents the structure of the DAC system. Section III
https://doi.org/10.1109/TCSII.2022.3188445. introduces the circuit implementation. Section IV presents the
Digital Object Identifier 10.1109/TCSII.2022.3188445 design results of the DAC. Section V concludes the work.
1549-7747 
c 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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4234 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO. 11, NOVEMBER 2022

Fig. 3. Splitting decoder with (a) traditional CMOS logic gates and (b) the
proposed data-transmission structure.

to <210 : 29 : 28 : 28 : 210 : 29 : 28 > ILSB controlled by

7-bit splitting codes <M 6 : · · · M 0 >. At the mid-code transi-
tion with <B11 : · · · B8 > switching between <0 : 1 : 1 : 1>
and <1 : 0 : 0 : 0>, the splitting codes <M 6 : · · · M 0 > switch
between <1 : 1 : 1 : 0 : · · · 0> and <1: · · · 1: 0: 0: 0>; only
28 ILSB current source flows are switched. According to [14],
the relationship between the number of the splitting decoding
Fig. 2. Major code transitions of (a) the binary-weighted current source array bits (m) and the RMS DNL can be expressed as follows:
and (b) the proposed splitting current source array.  σ (ILSB )
σRMS,DNL (ILSB ) = 2(N−m)+1 − 1 (2)
ILSB
II. A RCHITECTURE D ESIGN Thus, the RMS DNL of a “4 splitting bit + 8 binary bits”
Fig. 1 shows the structure of the proposed 12-bit current- segmented DAC at the mid-code transition is equivalent to
steering DAC. It is composed of an input register, a splitting that of a 9-bit binary current-steering DAC at the mid-code
decoder, a DEM decoder, a delay unit, switch drivers, and transition. As m increases, the DNL at the major transition
the current source array and switches. The four MSBs, B11 - decreases, as shows in (2), but the DNL at other transitions
B8 , are converted into 7-bit splitting codes, M 6 -M 0 . Then, the can hardly change, and the scale and delay of the splitting
DEM circuits operated as simple randomizer transform the decoder increase. To compromise the splitting decoder scale,
splitting codes into 15-bit random codes U 22 -U 8 . The eight DEM decoder scale, and SFDR improvement, the number of
least significant bits (LSBs), B7 -B0 , directly control the binary- splitting decoding bits is chosen to be four.
weighted current sources after a delay cell. Fig. 3 (a) shows a 4-7 splitting decoder with traditional
CMOS logic gates. The splitting decoding can be realized
mainly with AND and OR logic. Several transistors can be
III. C IRCUIT I MPLEMENTATION saved and the critical path can be shorten if the AND and
A. Splitting Decoding Approach OR gates are designed with a data-transmission topology in
Fig. 2 shows current source switching procedures of the Fig. 3 (b); thus, the circuit scale and delay of the decoder can
binary-weighted and the proposed splitting current-steering be significantly simplified. According to the circuit simula-
DACs at major transitions, with the schematic correspond- tion at a typical corner, the proposed splitting decoder reduces
ing to the four MSBs in a 12-bit DAC as an exam- the delay by 31.5%-63.6% compared with the decoder based
ple. For the binary-weighted current array in Fig. 2 (a), on the traditional CMOS logic gates when the supply voltage
with <B11 : · · · B8 > switched from <0 : 1 : 1 : 1> to ranges from 0.8 to 1.2 V and the temperature ranges from
<1 : 0 : 0 : 0>, all the current sources participate in −40 to 85 ◦ C. The low latency is beneficial for fast synchro-
switching. According to [14], the root mean square (RMS) nization of the control signals of the switches; thus, it improves
DNL at the mid-code transition for an N-bit binary-weighted the SFDR of the DAC. According to simulation results for
current-steering DAC can be as follows: “4 splitting bits + 8 binary bits” segmented DACs with differ-
ent splitting decoders, the proposed splitting decoder improves
 σ (ILSB )
σRMS_DNL (ILSB ) = 2N − 1 (1) the SFDR of the DAC by over 3 dB at an update rate of
ILSB 500 MS/s compared with the decoder based on traditional
logic gates.
In Fig. 2 (b), a splitting method is adopted to reduce the
maximum switching activity. The 211 ILSB current source con-
trolled by B11 is split into an array composed of <210 : · · · 28 > B. Simplified DEM Technique
ILSB , while the current sources steered by <B10 : B9 : B8 > With a smaller current source controlled by random code
remain unchanged. Thus, the current source array correspond- generated by the DEM decoder, a better random effect can
ing to <B11 : · · · B8 > is changed from <211 : · · · 28 > ILSB be achieved, which is supposed to be beneficial for SFDR

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TONG AND LIU: HIGH SFDR CURRENT-STEERING DAC 4235

Fig. 4. The simplified DEM decoder with two group division and two rotation stages.

Fig. 6. Floorplan of the current source array in the proposed DAC.

saved in total. Compared with DEM having rotation steps of 4,

2, and 1, the simulated SFDR just appears 0.51 dB attenuation.
From [16], several LSB codes with high switching activity can
Fig. 5. Output spectrum of different “4 splitting bits + 8 binary bits” be used as the rotation number for saving area. In this brief,
DACs (a) without DEM and with two-group division based DEM and (b) with B1 and B0 are used as the rotation number.
three-group and four-group division based DEM at an output signal frequency
of 6.34 MHz. For the DEM, each group is designed with a two-stage rotation
structure, and the random and systemic current source mismatches are both
included in this comparison. C. Current Sources Layout Design
Fig. 6 shows the floorplan of the current source array in the
proposed DAC. To reduce the systematic mismatch of cur-
optimization. However, the DEM decoder has a more com- rent sources, the QN random walk layout presented in [12] is
plex structure in this case, and the increased delay degrades used. The MSB current source array is composed of 15 × 28
the SFDR owing to the imperfect synchronization of the con- ILSB , which are controlled by U 22 –U 8 . The LSB current source
trol signals of switches. For achieving a compromise between array steered by the eight LSBs is composed of (28 –1) ILSB .
a relatively good random effect and low transmission delay, a Including a dummy unit current source, the total current
simplified DEM scheme is used. The 7-bit splitting codes are sources are 16 × 28 ILSB . Each current source group with
randomly decoded into 15-bit random codes, each of which 28 ILSB is further divided into 16 × 16 ILSB current sources.
is used to control a current source with 28 ILSB . To reduce Each unit square in Fig. 6 corresponds to 16 ILSB , so that we
the circuit scale and transmission delay, the DEM circuit is have 256 unit squares. The entire current source array is allo-
divided into two groups, as shown in Fig. 4; thus, the num- cated to four quadrants, and each quadrant is divided into four
ber of rotation stages and the maximum rotation step can be regions: A, B, C, and D, then each region has 16 unit squares
reduced [15]. Behavioral models of several “4 splitting bits marked with number 1 to 16. For each region, the Q2 random-
+ 8 binary bits” DACs with DEM involving different num- walk layout is performed for 16 × 16 ILSB current sources. In
ber of division groups and without DEM were constructed each quadrant, the regions A and C are located in the diagonal
for an SFDR comparison. The results of 1024-point FFT pro- directions of B and D, respectively. Four regions marked with
cessing with the unit current source mismatch σ (ILSB )/ILSB a same letter A, B, C, or D, is arranged in four quadrants with
of 0.01 LSB are compared in Fig. 5. The current source mis- common central symmetry method. The 28 ILSB current source
match between two groups is easier to be randomized than controlled by each bit of the DEM outputs is divided into
that in three-/four-group division DEM; thus, the group size 16 × 16 ILSB , corresponding to 16 above mentioned regions.
is selected to be two. The mismatch error profile with a 50% linear and 50%
The simplified DEM decoder is designed with two rotation quadratic joint error distribution adopted in [12] is used, and
stages with rotation steps of 4 and 2, thus, the maximum rota- the maximum systematic error of the unit current source is
tion is 6-runs. Compared with the DEM decoder presented determined to be 0.02 LSB for verifying the effectiveness of
in [10] with three rotation stages having rotation steps of 4, 2, the presented layout against systematic mismatch of current
and 1 (corresponding to a maximum rotation of 7 runs), 7 and sources. With this layout, the linear error can be eliminated,
8 multiplexers can be reduced for DEM Group-1 and Group- and the quadratic errors of all 16 current groups range from
2 because 1 rotation stage is saved; thus, 15 multiplexers are 0.012 LSB to 0.020 LSB, with an average value of 0.015 LSB.

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4236 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO. 11, NOVEMBER 2022

Fig. 9. Measured SFDR versus output signal frequency (a) of this chips
Fig. 7. Chip microphotograph of the proposed DAC. and (b) SFDR distribution for 10 chips at 500 MS/s.

the noise floor is increased because the harmonic energy has

been mixed into the floor noise.
Fig. 9 (a) is the measured SFDRs of this randomly selected
DAC with different output frequencies at 500 MS/s. With an
increase in the output-signal frequency, the SFDR decreased
owing to the reduced output impedance of the current
source array and transient-induced nonlinearity distortions.
The attenuation in the observed SFDR was only approximately
7 dB within the Nyquist bandwidth. With the application of
the DEM technique, the SFDR increased by approximately
8-10 dB throughout the Nyquist bandwidth, compared to that
of this DAC without DEM technique. Fig. 9 (b) summarizes
the SFDR distribution of 10 chips measured with DEM tech-
nique. The SFDR ranged from 70.43 dB to 74.76 dB with the
average of 72.94 dB at 8.30 MHz output signal frequency, and
ranged from 62.37 dB to 67.13 dB with an average value of
65.22 dB at 8.30 MHz output signal frequency.
To comprehensively analyze the performance of the DAC,
the figure-of-merit (FoM) values presented in [6] were used:
Fig. 8. Measured spectrum of one randomly selected DAC chip at 500 MS/s 2N · FS
and with output signal frequencies of (a) 8.30 MHz and (b) 225.10 MHz. FoM1 = (3)
Ptotal
SFDRDC −1.76 SFDRNyq −1.76
2 6.02 ×2 6.02 × FS
FoM2 = (4)
IV. R ESULTS AND D ISCUSSION Ptotal − 0.5 × Iload × Rload
2

The proposed 12-bit splitting-binary segmented current-

The performance of the proposed 12-bit DAC was com-
steering DAC was fabricated in a 0.18-µm CMOS process.
pared with that of the state-of-the-art designs presented
A micrograph of the chip is shown in Fig. 7. The active area
in Table I. The current source mismatch and transient-
was 452.82 µm × 491.76 µm. The full-scale output current
induced nonlinearity distortions were optimized to enhance
of the DAC was 6 mA, and the peak-to-peak voltage swing
the SFDR in [1], [2], [6], [15] and [17]–[19]. The DACs
was 600 mV when driving 50  double-terminated off-chip
presented in [1]–[2], [6], [18], and [19] achieved faster sam-
resistors. With a 1.2 V digital supply and a 1.8 V analog sup-
pling using advanced CMOS processes, but the proposed DAC
ply, the power consumption of the DAC was 12.2 mW; only
consumed less power. In [10], the DEM technique was used to
1.39% was consumed by the DEM decoding circuit owing
improve the SFDR of the DAC, but severe attenuation in the
to the simplified structure, and only 0.65% was consumed
SFDR occurred at the Nyquist frequency. The DAC in [11]
by the splitting decoder owing to its data transmission based
with a nested-segmentation DEM structure has more complex
topology. The other power consumption percentages were as
logic, limiting the speed and increasing the power consump-
follows: 87.4% for the current source and switch array, 2.61%
tion. Fig. 10 shows a comparison of FoM1 and FoM2 with
for input registers, and 7.92% for switch drivers.
respect to the active area between existing DACs and the
Fig. 8 shows the measured output spectrum of one randomly
proposed one. The proposed DAC achieved competitive FoM
selected DAC chip at 500 MS/s with output-signal frequencies
values even with a submicron CMOS process.
of 8.30 and 225.10 MHz. By using the DEM technique, the
measured SFDR of this DAC with 8.30 MHz output frequency
increased from 63.18 dB to 73.30 dB. Additionally, the mea- V. C ONCLUSION
sured SFDR with a 225.10 MHz output-signal frequency was A current-steering DAC with “4 splitting bits + 8 binary
58.59 dB without DEM, and it increased to 66.64 dB by using bits” segmented structure is proposed along with a splitting
the DEM technique. Although the DEM technique suppressed decoding method having a reduced circuit scale compared with
the harmonic distortion caused by current source mismatch, unary decoding. Owing to its data-transmission topology, the

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TONG AND LIU: HIGH SFDR CURRENT-STEERING DAC 4237

TABLE I
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