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International Journal of Advanced Research in Management, Architecture, Technology and

Engineering (IJARMATE)
Vol. 2, Issue 3, March 2016

A Novel 10 Bit Current Steering CMOS

Segmented Digital to Analog Converter
Induvathani.L1, Karthikeyan.S2
PG Scholar, Department of ECE, Vandayar Engineering College, Thanjavur, India 1
Assistant Professor, Department of ECE, Vandayar Engineering College, Thanjavur, India 2

bench and results of the DAC are described in section IV.

Abstract— The design of 10 bit current steering digital to
analog converter consisting of a segmented architecture in 90 II. 10 BIT CURRENT STEERING DAC OVERVIEW
nm CMOS technology. The resolution for this design is 10 bits,
segmented into 6 thermometer encoded current cells and 4 The current steering DAC works by “steering” the current
binary weighted current cells. Thermometer encoding is used between a set of differential outputs. Reference currents are
instead of binary coded decimal to reduce glitches since only one created by several current cells and are summed at the outputs
bit changes at a time. The simulation results show the input [3]. To achieve high speed and to reduce glitches, a binary to
bandwidth of the DAC is 250 MHz. This work presented a good thermometer encoder is used [4, 5]. The output from the
performance compared with other researches in DNL, INL and thermometer encoder turns on the appropriate current cells to
Power Consumption also speed. The design methodology of the produce the analog output. An example of 3 binary bits to 7
sub-components such as current cell, thermometer encoder, and
bit thermometer code is shown in Table 1. This architecture is
bias circuits. A number of different DAC architectures were
examined, each with their own advantages and disadvantages. Also known as a unary weighted DAC. For high resolution
The current steering architecture is the preferred high speed designs the amount of current cells becomes an issue because
architecture. One of the trades offs in DAC design is the it increases complexity of the layout [6]. A solution to this
resolution vs. speed. As the resolution increases, it becomes problem is to trade off some speed of the fully thermometer
harder to achieve high bandwidth. The resolution for this design encoded design for reduced complexity by segmenting the
is 10 bits. DAC. This is done by using thermometer encoding for the
MSBs and using a binary weighted sub-DAC for the LSBs.
Index Terms— DAC, current steering, high speed, current For the DAC presented, segmentation was used to obtain 6
cell design.
thermometer encoded MSBs, and 4 binary weighted LSBs.
I. INTRODUCTION TABLE I. BINARY VS. THERMOMETER CODE
Data converters are one of the most important types of
circuits because they bridge the gap between the analog and Decimal Binary Thermometer
digital domains. The speed of the converter is often the 0 000 0000000
bottleneck in high bandwidth applications. As the bandwidth 1 001 0000001
requirements for devices keep increasing, the importance of 2 010 0000011
data converters also rises. High bandwidth digital to analog
3 011 0000111
converters (DAC) have been constructed using processes
such as SiGe [1] or GaAs [2] with the prevalence of systems 4 100 0001111
on a chip it is very advantageous to design a high speed 5 101 0011111
converter using standard CMOS processes. 6 110 0111111
A number of different DAC architectures were examined, 7 111 1111111
each with their own advantages and disadvantages. The
current steering architecture is the preferred high speed The unit current cells are arranged in a matrix pattern as
architecture. One of the trade offs in DAC design is the given in Fig. 1. To control the current cells, two thermometer
resolution vs speed. As the resolution increases, it becomes encoders are used. One encoder addresses the column and the
harder to achieve high bandwidth. The resolution for this other addresses the appropriate row in the current cell matrix.
design is 10 bits. The goal for the DAC is to be able to achieve Since the segmentation for the MSBs is 6, the first three most
400 MHz input frequency, with hopes that higher speeds can significant bits (B9, B8, B7) of the inputs are sent to the row
be achieved with some circuit optimization. Section II encoder, the next three most significant inputs (B6, B5, B4)
provides an overview of the current steering DAC are sent to the column encoder. With three digital inputs
architecture. More detailed discussion of the sub-components going to the encoder, 8 thermometer outputs are produced. By
of the DAC is presented in section III. The design of test using this segmentation scheme the DAC has a 8x8 unit

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Vol. 2, Issue 3, March 2016

current cell matrix. circuits. Since the switches are differential only one is turned
The four least significant bits (B3-B0) digital inputs are on at a given time. The input Z turns on transistor M1,
sent to the binary weighted sub-DAC. A dummy encoder is allowing current flow from Iout to ground. When Z is enabled,
placed between the digital input and the current cells to add Z is turned off directing the current through complementary
some delay so the binary weighted and thermometer encoded output Iout. In order to sink the appropriate amount of current
cells are synchronized. The binary weighted section contains a bias voltage is applied to the gate of the current sink. With
four current cells producing the currents I, 2I, 4I, 8I. The the cascode current sink two bias voltages are needed.
output from the binary weighted sub-DAC is connected to the
output from the thermometer encoded cells to produce the
analog output. Two load resistors are connected to the
positive and negative output terminals to convert the output
current to voltage. The supply voltage is connected to one end
of the load resistor while the current cells are connected with
the other end of the resistor. As the current is drawn through
the load resistor to the current cells a voltage is created. The
final DAC output is found by subtracting the voltage drop
across the load resistor from Vdd.

Figure 2. Differential switches and cascode current sinks.

Accuracy of the current mirrors is crucial to the

performance of the converter. One issue with the current
mirror is that as Vds from M1 to M4 varies, the amount current
Figure 1. Block diagram of current steering DAC. sinked varies. This is very problematic because the current
cells need to output a constant current in order to maintain
The resolution for this converter is 10 bits, which means good accuracy. The output of three different current sink
there will be a maximum of 1024 voltage levels that needs to architectures is shown in Fig. 3. The output current is obtained
be produced. The full scale range of the output is from 0 to by sweeping the drain voltage seen by the switch (Vcell) and
725 mV. By dividing 725 mV by 210, the LSB for the DAC is current sink transistors in Fig. 3. Since the current cell is
found to be 0.7 mV. Load resistors are connected to each of directly connected to the output of the DAC, as the output
the output lines. The resistance is set to be 50 ohm, which voltage changed, the Vcell across the switching transistors and
creates a unit current I of 14 uA. The rest of the current cells current sinks varies.
produce 28 uA, 56 uA, 112 uA, and 226 uA. The final DAC output is obtained from subtracting the
voltage drop across the load resistor by the supply voltage.
III. SUB-CIRCUIT DESIGN The voltage divider caused by the load resistors means that
The current steering architecture has several the analog output Vout will be in the range of 0 to 725 mV.
sub-components that need to be carefully designed. The key However, the drain voltage across the current cells will
component is the current cell, which includes a differential operate from 1.2 V to 475 mV. When analyzing the
pair of switches, and a current mirror to produce the reference performance of the current cells, 1.2 V in Fig. 3 corresponds
current. The next set of components is the thermometer to the analog output of 0 V since all of the Vdd from the load
encoder and local decoders. Finally bias circuits are used to resistor is being sinked by the current cell. At full scale output,
provide the correct bias voltage to all of the current cells. the Vdd from the load resistor is split between Vout and the
current cells, causing the current cell drain voltage to be
A. Current Cell 475mV.
The current cells are made up of a pair of differential The first two architectures compared in Fig. 3 are the basic
switches, and a current sink which can be seen in Fig. 2. A single transistor current sink and the cascode current sink. It
single transistor can be used as a current sink, but a cascode was observed that the standard current sink varies 33 uA as
current sink is used in this design to increase current sink Vcell changes from 1.2 V to 475 mV. The output current for
accuracy. The reference current is created by using NMOS the cascode current sink changes by 22 uA in the same current
transistors to sink Vdd from the load resistors to ground. The cell operating range. The basic current cell does not output a
switches are controlled by the thermometer encoder and latch constant current over the operating range. This is caused by
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Vol. 2, Issue 3, March 2016

the single transistor current sink having low output to be biased at voltage higher than the Vdd of 1.2 V. A bias
impedance. The cascode current sink produces a more voltage of 1.8 V is chosen, increasing the headroom. The
constant current since the extra cascode transistor increases higher headroom allows the full-scale DAC output of 725 mV
the output impedance [7, 8]. The problem with both current to be achieved by having the current cell operate from 1.075
sink designs is that as Vcell approaches 475 mV, the transistors V to 1.8 V.
start to go out of saturation. This causes the reference current The output current of the modified current cell is shown in
to drop which will cause large errors in the DAC output. Fig. 3. This design only varies by 192 nA across the operating
range which is a large improvement over the previous two
architectures. The accuracy of the DAC reference currents are
often measured in how much it deviates from the LSB. The
LSB current is typically allowed to be off by plus or minus .5
LSB which is 7 uA in this design. Based on the results in Fig.
4, the basic current sink has an error far greater than .5 LSB.
The cascode current sink has an error equal to one LSB. The
cascode switch current sink easily meets the requirement of .5
LSB.
In the thermometer encoded section of the DAC, 63
current cells are used, each producing a current of 16I. The
binary weighted portion contains four current cells, outputting
Fig. 3. Comparison of output currents of the different current sink I, 2I, 4I, and 8I. The thermometer encoded current cell
architectures as the drain voltage changes
includes a local encoder circuit, a latch, the current switch,
and the current sink. The binary weighted current cell has a
The current cell design can be further improved by latch, current switch, and current sink. To obtain the correct
cascoding the switch transistors, which can be seen in Fig. 4. reference current in the different current cells the width of the
This buffers the switches from the changing output current sink transistors are adjusted. To increase the current
capacitance which reduces glitches and increases switching from I to 2I the current sink transistor width is roughly
speed. Charge is stored on the node between the current doubled. Each current cell receives a bias voltage to produce
source and switching transistors [9]. When the switch turns on the correct reference current. For the binary weighted and
the capacitance is discharged to the output. The amount of thermometer encoded current cells, the current sink Vbias is
charge dissipated to the output depends on how many current 450 mV, the current sink cascode transistor Vbias2 is 1.0 V.
cells are currently active at a given time.

B. Current Cell Biased Circuit

Bias circuitry needs to be designed in order to provide the
appropriate Vbias to the current mirrors. The bias circuit can be
localized to each current cell or there can be global bias
circuits that supply a large amount of the cells. With the large
amount of current cells present having a single bias circuit
would mean a large amount of interconnect would be needed.
The interconnect could be sensitive to all the switching wires
nearby which could cause inaccuracies in the bias voltages.
Another consideration for the bias circuit is its sensitivity to
power supply fluctuations. A simple voltage reference circuit
can be made by using a PMOS as a resistor and a NMOS as a
current sink. The downside to this approach is that it is
directly dependent on Vdd. A more advanced bias circuit is
presented in Fig. 5. This design can produce a constant bias
Figure 4. Modified cascode switch current sink.
voltage even if the power supply varies [7].

One of the drawbacks of having a Vdd of 1.2 V is that it The design works by scaling the size of M2 so that is
limits the headroom for the current cells. Even with the larger than M1. The resistor value is adjusted to obtain the
cascoded current source there is only a narrow voltage range correct reference current. The transistors MSU1, MSU2,
where the transistors can operate in saturation. A highly MSU3, are added as a start-up circuit. If M1 and M2 are
accurate current cell is created by modifying the cascade grounded, MSU3 will be enabled, sending current to M1 and
switch transistor seen in Fig 4. To improve the accuracy of the M2. Once the bias circuit is in the desired state MSU3 turns
reference current cell, the cascoded switch is replaced with a off.
thick gate oxide transistor [9]. This allows the cascode switch

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Vol. 2, Issue 3, March 2016

Figure 5. Supply independent bias circuit. Figure 7. Full scale output sweep of DAC.

C. Thermometer Encoding and Local Decoder Design

The INL and DNL were measured by using modules
Two thermometer encoders are used in the DAC, one to provided in the ahdlLib library from Cadence. The INL of the
address the columns of the current cell matrix and the other to converter is seen in Fig. 8 and the DNL is presented in Fig. 9.
address the rows. The encoders have three binary inputs and It can be seen that the max INL is 0.41 LSB and the worst
eight thermometer outputs. To obtain the logic for the outputs DNL is -0.031 LSB.
Karnaugh maps were used. These logic gates were built using
standard static CMOS logic.
The encoders can be optimized to reduce delay from the
digital input to the current cells. If the static CMOS gates are
too slow they could potentially be replaced with pass
transistor logic. Buffers are added in some of the gate paths in
order to equalize the delay between all the thermometer
outputs.
The thermometer encoded current cells all include a local
decoder and latch circuits. Fig. 6 shows the logic diagram for
the local decoder and latch circuits. The local decoder takes
the columni, rowi, and rowi- 1 outputs from the thermometer
encoder and determines if the current cell should be turned on.
In order to turn on the current cell, rowi or columni both have
to be logic one, which is then sent to an NAND function with
Figure 8. Max INL 0.41 LSB.
rowi-1. The decoder logic was implemented in standard static
CMOS with an inverter to get the differential signals for the
current switches. A high speed master-slave latch was
constructed to synchronize all the signals. This is placed
between the local decoder and the current switches.

Figure 6. Local decoder and latch.

IV. DAC RESULTS

With all the sub-components completed the DAC was
wired together. A 50 ohm load resistor was placed on each of Figure 9. Max DNL -0.031 LSB.
the output lines with one terminal connected to power supply
in order to convert the output current into voltage. The plot in To determine the transient performance of the DAC, the
Fig. 7 shows the full scale range output of the converter. The converter needed to reproduce a sine wave. An ideal ADC
clock frequency was set to 500 MHz, and the LSB of the was created so that a sign input could be given, then the ADC
digital input was pulsed at a frequency of 250 MHz. would output the corresponding digital codes to the DAC.

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Vol. 2, Issue 3, March 2016

The ideal ADC was created by using a tool built into REFERENCES
Cadence called Model writer. This tool allows the user to [1] S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering
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[2] Choe, Myung-Jun; Baek, Kwang-Hyun; Teshome, M. A 1.6-GS/s
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from the DAC. The input signals frequency was 125 MHz, dis-sertation, Thesis no. 667, Linköping Univ., Linköping, Sweden,
while the clock pulsed at 1 GHz. The spectrum plot of the 2001.
[4] Myderrizi and A. Zeki, "Current-Steering Digital-to-Analog
DAC can be seen in Fig. 11. The clock frequency was set to 1 Converters: Functional Specifications, Design Basics, and Behavioral
GHz with a sine input of 250 MHz. The SFDR was measured Modeling," IEEE Antennas and Propagation Magazine, Vol. 52, No.4,
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[5] K. O. Anderson, Modeling and Implementation of Current-Steering
Digital-to-Analog Converters, Linköping Studies in Science and
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REFERENCES

L.Induvathani received the B.E degree in

Electronics and Communication Engineering from
Kings Engineering College, Tamilnadu, India in
2014 and the master’s degree in VLSI Design from
Vandayar Engineering College, Tamilnadu, India
in 2016. Her area of interest relies on Digital to
Analog Converter.
Figure 11. DFT plot of DAC with input frequency of 250 MHz.
S.Karthikeyen received B.E degree in Electronics
and communication engineering from Pavendhar
V. CONCLUSION Bharathidasan College of Engineering
In this paper the design of a high speed 10 bit digital to &Technology, Tamilnadu, India in 2008 and the
analog converter is presented. This design utilizes the current
Master’s degree in communication systems from
steering architecture in order to operate at high speeds. The
design methodology for each of the sub-components was Adhiyamaan College of engineering, Tamilnadu,
presented. The INL and DNL of the converter were measured India in 2013.He is currently working as an
to be 0.41 LSB and -0.031 LSB, respectively. The SFDR of Assistant Professor & Head of the department of
the converter was measured to be 68.62 dB with an input Electronics and Communication Engineering,
frequency of 250 MHz and a clock frequency of 1 GHz.
Vandayar Engineering College, Tamilnadu, India.
His area of interest relies on Antenna and wave
propagation.

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