Moschip Placement Drive: 2-Week Full Preparation Strategy & Complete Syllabus Notes
Overview:
Moschip selection involves two rounds: 1. Prelims (Online MCQ Test) 2. Mains (Offline Subjective Exam)
Syllabus Breakdown:
Prelims (MCQs - Online):
• Circuit Networks
• Electronic Devices and Circuits (EDC)
• CMOS Circuit Logic
• Digital Design
• Aptitude
Mains (Subjective - Offline):
• Two Papers: Analog (1.5 hrs), Digital (1.5 hrs)
• Topics same as prelims but descriptive solving
14-Day Study Plan
Week 1: Concept Clarity + MCQ Practice
Day Topics Checklist
Day 1 Digital Basics Logic Gates, K-map, Boolean Algebra
Day 2 Combinational/Sequential MUX/DEMUX, Flip-Flops, FSMs
Day 3 Analog - Diodes PN Junction, Zener, Clipping/Clamping
Day 4 BJTs & FETs Biasing, CE Amplifier, Characteristics
Day 5 CMOS Inverter VTC, CMOS NAND/NOR, Noise Margins
Day 6 Networks Thevenin/Norton, KVL/KCL, Transients
Day 7 Aptitude Time-Work, Ratios, S.I/C.I, Pipes
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Week 2: Subjective Focus + Revision
Day Topics Checklist
Day 8 Analog Subjective Diodes, Op-Amps, BJT Biasing
Day 9 Digital Subjective FF Conversion, FSM Design
Day 10 CMOS Subjective Logic Gates, Delay, Stick Diagram
Day 11 Networks Subjective RLC Transients, 2-Port Networks
Day 12 Mock MCQ Test Full Prelims + Aptitude Simulation
Day 13 Mock Subjective Test Analog & Digital Papers (1.5 hrs each)
Day 14 Final Revision Formula sheet, Notes, Weak Topics
Detailed Notes for Full Syllabus
✅ DIGITAL DESIGN
• Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
• Boolean Laws: Idempotent, Complement, DeMorgan’s, Distributive
• K-Map Simplification: SOP, POS forms; 2- to 4-variable maps
• Combinational Circuits: Adder, Subtractor, Multiplexer, Demux, Encoder, Decoder
• Sequential Circuits: Flip-Flops (SR, JK, D, T), Latches, Counters (Async, Sync), Shift Registers
• FSM: Mealy and Moore models, State diagrams, State reduction
✅ CMOS CIRCUIT LOGIC
• CMOS Inverter: VTC curve, noise margin (NMH, NML), switching threshold
• NAND/NOR using CMOS: Pull-up (PMOS), Pull-down (NMOS)
• CMOS Delay: tpHL, tpLH; Delay ∝ CL × V × V
• Power Dissipation: Dynamic and Static Power
• Stick Diagrams and Layout Basics: Euler paths, design rules (basic level)
✅ ANALOG ELECTRONICS (EDC)
• Diodes: Characteristics, Zener breakdown, Clipping/Clamping circuits, Rectifiers
• BJTs: Modes of operation, CE configuration, Biasing methods (fixed, voltage divider)
• FETs: JFET and MOSFET operation, transfer characteristics, high input impedance
• Amplifiers: CE, CC, CB configurations, Gain, Input/Output resistance
• Op-Amps: Ideal vs practical, inverting/non-inverting amplifiers, integrator/differentiator
✅ CIRCUIT NETWORKS
• Basic Laws: Ohm’s Law, KVL, KCL
• Analysis Methods: Nodal, Mesh analysis
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• Theorems: Superposition, Thevenin, Norton, Maximum Power Transfer
• Transient Analysis: RC, RL, RLC circuits – natural and step response
• Resonance: Series and Parallel resonance, quality factor
• 2-Port Networks: Z, Y, h, and T-parameters; interconnections
✅ APTITUDE (QUANT + LOGICAL)
• Time & Work: Work = Rate × Time, LCM method
• Percentages: Profit/Loss, Discount, Successive % changes
• Ratios & Proportions: Simple and Compound Ratios
• Simple & Compound Interest: SI = (P×R×T)/100, CI = P(1+R/100)^T
• Speed, Distance & Time: Relative speed, trains, boats
• Pipes & Cisterns: Inlet = +, Outlet = –
• Reasoning: Coding-decoding, Directions, Puzzles, Blood Relations
✅ ADVANCED ANALOG & MIXED SIGNAL (For Interviews)
• ADC/DAC Basics: Types – Flash, SAR, Weighted resistor
• PLLs: Phase-locked loop basics, lock range, applications
• SerDes: Serializer/Deserializer concept, use in high-speed links
• CDR: Clock and data recovery concept
• Bandgap Reference: Provides constant voltage independent of supply/temp
• Voltage Regulators: Linear and switching regulators
Practice Questions
Digital MCQs
1. Output of NAND(1,1)?
2. How many states in 4-bit counter?
3. SOP of A + A’B?
4. JK FF toggle condition?
Analog MCQs
1. Silicon diode forward voltage?
2. CE amplifier phase shift?
3. MOSFET functions?
CMOS MCQs
1. Faster logic: CMOS or TTL?
2. Power usage in CMOS?
3. Define CMOS VTC.
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Aptitude MCQs
1. A: 6 days, B: 12 → together?
2. 180m train @ 60kmph → pole?
3. A:B = 3:2, B:C = 4:3 → A:C?
Subjective Questions – Analog
1. Design clipper at 5V.
2. Explain CE amplifier.
3. Op-Amp: Inverting mode working.
Subjective Questions – Digital
1. 3-bit synchronous counter using T FF
2. Minimize F(A,B,C)=Σ(1,3,5,7)
3. FSM for even number detector
YouTube Channels for Prep
Topic Channels
Analog Neso Academy, All About Electronics
Digital Neso Academy, Gate Smashers, ECEBuds
CMOS VLSI Academy, VeeLSI
Networks Gate Wallah, Neso Academy
Aptitude Chandan Logics, TalentBattle
Final Tips:
• Practice clean circuit drawings for Mains
• Focus extra on Digital + CMOS
• Revise formula sheets daily
• Use mocks for self-evaluation
You are ready to crack Moschip! 💪
