DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
MADAN MOHAN MALAVIYA UNIVERSITY OF TECHNOLOGY, GORAKHPUR
ASSIGNMENT 2 SOLUTION
SUBJECT- VLSI DESIGN BEC-401
FACULTY- PROF. R. K. CHAUHAN
Question 1
MOS inverters are the basic building block of VLSI design. The basic MOS inverter contains a resistor
as a load device. Explain how does the resistive load affect noise margin of the inverter.
Solution :- The logic symbol and the truth table of the ideal inverter are shown in Fig. 5.1. In MOS inverter
circuits, both the input variable A and the output variable B are represented by node voltages, referenced to
the ground potential. Using positive logic convention, the Boolean (or logic) value of "1" can be represented
by a high voltage of VDD, and the Boolean (or logic) value of "0" can be represented by a low voltage of 0.
The DC voltage transfer characteristic (VTC) of the ideal inverter circuit is shown in Fig. 5.2. The voltage Vt h
is called the inverter threshold voltage. Note that for any input voltage between 0 and Vt h = VDD/2, the output
voltage is equal to VDD (logic" 1 ). The output switches from VDD to 0 when the input is equal to Vth. For any
input voltage between Vth and VDD, the output voltage assumes a value of 0 (logic "0"). Thus, an input voltage
0 < Vi. < Vth is interpreted by this ideal inverter as a logic "0," while an input voltage Vth < V DD is interpreted
as a logic " 1." The DC characteristics of actual inverter circuits will obviously differ in various degrees from
the ideal characteristic shown in Fig. 5.2.
The basic structure of the resistive-load inverter circuit is shown in Fig. 5.7. an enhancement-type nMOS
transistor acts as the driver device. The load consists of a simple linear resistor, RL. The power supply voltage
of this circuit is VDD. Since the following analysis concentrates on the static behavior of the circuit, the output
load capacitance is not shown in this figure. The drain current ID of the driver MOSFET is equal to the load
current R in DC steady-state operation. To simplify the calculations, the channel-length modulation effect will
be neglected in the following, i.e., ƛ = 0. Also, note that the source and the substrate terminals of the driver
transistor are both connected to the ground; hence, VSB = 0. Consequently, the threshold voltage of the driver
transistor is always equal to VT0.
For input voltages smaller than the threshold voltage Vth, the transistor is in cut-off, and does not conduct any
drain current. Since the voltage drop across the load resistor is equal to zero, the output voltage must be equal
to the power supply voltage, VDD. As the input voltage is increased beyond VT0, the driver transistor starts
conducting a nonzero drain current. Note that the driver MOSFET is initially in saturation, since its drain-to
source voltage. (VDs = Vout) is larger than (Vin-VT0). Thus,
With increasing input voltage, the drain current of the driver also increases, and the output voltage V out starts
to drop. Eventually, for input voltages larger than Vout + VT0 the driver transistor enters the linear operation
region. At larger input voltages, the transistor remains in linear mode, as the output voltage continues to
decrease.
The various operating regions of the driver transistor and the corresponding input-output conditions are listed
in the following table.
Figure 5.8 shows the voltage transfer characteristic of a typical resistive-load inverter circuit, indicating the
operating modes of the driver transistor and the critical voltage points on the VTC.
Calculation of VOH
First, we note that the output voltage Vout is given by
Question 2
How is the noise margin defined in a CMOS inverter? How do you calculate the noise margins (NMH
and NML) for a CMOS inverter?
Solution :- The CMOS inverter consist of a consists of an enhancement-type nMOS transistor and an
enhancement-type pMOS transistor, operating in complementary mode. This configuration is called
Complementary MOS (CMOS). The circuit topology is complementary push-pull in the sense that for high
input, the nMOS transistor drives (pulls down) the output node while the pMOS transistor acts as the load,
and for low input the pMOS transistor drives (pulls up) the output node while the nMOS transistor acts as the
load. Consequently, both devices contribute equally to the circuit operation characteristics.
The CMOS inverter has two important advantages over the other inverter configurations. The first and perhaps
the most important advantage is that the steady-state power dissipation of the CMOS inverter circuit is
virtually negligible, except for small power dissipation due to leakage currents. In all other inverter structures
examined so far, a nonzero steady-state current is drawn from the power source when the driver transistor is
turned on, which results in a significant DC power consumption. The other advantages of the CMOS
configuration are that the voltage transfer characteristic (VTC) exhibits a full output voltage swing between
0v and VDD, and that the VTC transition is usually very sharp. Thus, the VTC of the CMOS inverter resembles
that of an ideal inverter.
Circuit Operation
Question 3
What are the key parameters that define the switching characteristics of a CMOS inverter? How do
you calculate the propagation delay of a CMOS inverter?
Solution :-
Question 4
Derive the expression for delay time in CMOS inverter design.
Solution :-
Question 5
A VLSI designer aims to design an inverter. Suggest the most efficient inverter design through a
comparison of different MOS based inverters.
Solution :-
1. Advantages and disadvantages of Resistive load inverter
Advantages:
Simple Design and Operation
efficient Power Conversion
Reduced Electrical Noise
Lower Complexity of Load Management
Stable Performance
Disadvantages
Limited Load Compatibility, Not Suitable for All Loads
Limited Overload Handling
Heat Generation
Dependence on Load Type
Lack of Advanced Features
2. Advantages and disadvantages of enhancement-load n-type MOSFET as a load
Advantages
The main advantage of using a MOSFET as the load device is that the silicon area occupied
by the transistor is usually smaller than that occupied by a comparable resistive load.
Inverter circuits with active loads can be designed to have better overall performance
compared to that of passive load inverters.
In a chronological view, the development of inverters with an enhancement type MOSFET
load precedes other active load inverter types, since its fabrication process was perfected
earlier.
Disadvantages
The most significant drawback of this configuration is the use of two separate power supply
voltages. In addition, both types of inverter circuits suffer from relatively high stand-by (DC)
power dissipation; hence, enhancement load nMOS inverters are not used in any large scale
digital applications.
3. Advantage and disadvantages of CMOS inverter
Advantages
CMOS inverters consume very little power when not switching because only leakage currents
are present in the steady state. This is due to the complementary nature of PMOS and NMOS
transistors, which ensures that one is always off while the other is on.
MOS inverters have a high noise margin, making them less susceptible to noise and ensuring
reliable operation even in the presence of small fluctuations in input signal levels.
CMOS inverters can switch between states very quickly, which contributes to high-speed
digital circuit performance. This is partly because CMOS technology allows for fast
transition times due to the low capacitance in the gate region.
CMOS technology scales well with advances in semiconductor fabrication, allowing for the
development of smaller and more efficient devices. This scalability has been a key factor in
the progression of Moore's Law.
Due to their low static power consumption, CMOS inverters generate less heat compared to
other types of inverters, which helps in reducing cooling requirements and improves overall
system reliability.
Disadvantages
Designing CMOS circuits, especially when scaling to very small geometries, can be
complex. The design rules need to account for various parasitic effects and ensure proper
transistor sizing and layout.
While CMOS inverters have low static power consumption compared to other
technologies, leakage currents can still be significant, especially in deep submicron
processes. This becomes more problematic as devices become smaller.
CMOS inverters require more silicon area compared to other logic families like TTL
(Transistor-Transistor Logic). This can be a concern in highly integrated circuits where
area efficiency is crucial.
The performance of CMOS inverters is highly dependent on the supply voltage.
Variations in supply voltage can affect the performance, switching speed, and overall
stability of the inverter.
Although static power consumption is low, dynamic power consumption can be higher
when the inverter switches states frequently. This is due to the charging and discharging
of load capacitances.
Question 6
Why is it essential to design a super buffer when dealing with large capacitive loads in high-speed
digital circuits?
Solution :-
