CMOS Inverter
• All of the inverter circuits considered so far
consisting of an enhancement-type nMOS driver
transistor and a load device which can be a resistor,
an enhancement-type nMOS transistor, or a
depletion-type nMOS transistor acting as a nonlinear
resistor.
• In this general configuration, the input signal is
always applied to the gate of the driver transistor,
and the operation of the inverter is controlled
primarily by switching the driver.
CMOS Inverter
• CMOS Inverter consists of an enhancement-type nMOS
transistor and an enhancement-type pMOS transistor,
operating in complementary mode
• This configuration is called Complementary MOS (CMOS).
CMOS Inverter
• The circuit topology is complementary push-pull
• For high input, the nMOS transistor drives
(pulls down) the output node while the pMOS
transistor acts as the load
• For low input the pMOS transistor drives (pulls up)
the output node while the nMOS transistor acts as
the load.
• Consequently, both devices contribute equally to the
circuit operation characteristics.
CMOS Inverter
• The CMOS inverter has two important advantages
over the other inverter configurations.
• The first advantage is that the steady-state power
dissipation of the CMOS inverter circuit is virtually
negligible, except for small power dissipation due to
leakage currents.
• In all other inverter structures a nonzero steady-
state current is drawn from the power source when
the driver transistor is turned on, which results in a
significant DC power consumption.
CMOS Inverter
• The other advantages of the CMOS configuration are
that the voltage transfer characteristic (VTC) exhibits a
full output voltage swing between 0 V and VDD, and
that the VTC transition is usually very sharp.
• Thus, the VTC of the CMOS inverter resembles that of
an ideal inverter.
• Since nMOS and pMOS transistors must be fabricated
on the same chip side- by-side, the CMOS process is
more complex than the standard nMOS-only process.
CMOS Inverter
• In CMOS inverter the input voltage is connected to the
gate terminals of both the nMOS and the pMOS
transistors.
• Thus, both transistors are driven directly by the input
signal, Vin.
• The substrate of the nMOS transistor is connected to
the ground, while the substrate of the pMOS transistor
is connected to the power supply voltage, VDD.
• Since VSB = 0 for both devices, there will be no
substrate-bias effect for either device
CMOS Inverter
• From the circuit diagram of Fig.
CMOS Inverter
Case1:
When the input voltage is smaller than the nMOS
threshold voltage, i.e., when Vin < VT0,n the nMOS transistor
is cut-off. At the same time, the pMOS transistor is on,
operating in the linear region.
The drain currents of both transistors are approximately
equal to zero (except for small leakage currents)
.
CMOS Inverter
• When the input voltage exceeds (VDD + VT0,P) the pMOS
transistor is turned off.
• In this case, the nMOS transistor is operating in the linear
region, its drain to-source voltage is equal to zero
The output voltage of the circuit is
CMOS Inverter
• The nMOS transistor operates in saturation if Vin > VT0,n and if
the following condition is satisfied:
• The pMOS transistor operates in saturation if Vin < (VDD +
VT0,P), and if :
CMOS Inverter
CMOS Inverter
CMOS Inverter
• In a CMOS inverter operating in steady-state, the
drain current of the nMOS transistor is always equal
to the drain current of the pMOS transistor
CMOS Inverter
• The inverter threshold voltage is defined as Vth = Vin =
Vout.
• Since the CMOS inverter exhibits large noise margins
and a very sharp VTC transition, the inverter threshold
voltage emerges as an important parameter
characterizing the DC performance of the inverter.
• For Vin = Vout, both transistors are expected to be in
saturation mode.
• Current drawn from the power source during
transition reaches its peak value when Vin = Vth.
CMOS Inverter
CMOS Inverter
• For an ideal inverter the switching threshold
voltage is defined as
CMOS Inverter
Symmetric CMOS inverter
Symmetric CMOS inverter
