Physics of gate leakage current in N-polar InAlN/GaN heterojunction field effect

transistors
Arunesh Goswami, Robert J. Trew, and Griff L. Bilbro

Citation: Journal of Applied Physics 116, 164508 (2014); doi: 10.1063/1.4900581

View online: http://dx.doi.org/10.1063/1.4900581
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 JOURNAL OF APPLIED PHYSICS 116, 164508 (2014)

Physics of gate leakage current in N-polar InAlN/GaN heterojunction field

effect transistors
Arunesh Goswami, Robert J. Trew, and Griff L. Bilbro
ECE Department, Box 7911, North Carolina State University, Raleigh, North Carolina 27695-7911, USA

(Received 7 July 2014; accepted 16 October 2014; published online 29 October 2014)
A physics based model of the gate leakage current in N-polar InAlN/GaN heterojunction field
effect transistors is demonstrated. The model is based on the space charge limited current flow
dominated by the effects of deep traps in the InAlN surface layer. The model predicts accurately
the gate-leakage measurement data of the N-polar InAlN/GaN device with InAlN cap layer. In the
pinch-off state, the gate leakage current conduction through the surface of the device in the drain
access region dominates the current flow through the two dimensional electron gas channel. One
deep trap level and two levels of shallow traps are extracted by fitting the model results with mea-
surement data. VC 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4900581]

I. INTRODUCTION is characterized by three regions in the I-V plot: a shallow

trap region, a high field region and a velocity saturation
GaN based heterojunction field effect transistors
region.9 The I-V characteristics of the InAlN/GaN HFET
(HFETs) are attractive options for high power and high fre-
gate leakage indicate a threshold voltage after which the
quency applications. The excellent performance of the GaN
leakage current abruptly increases with the increase in gate-
HFETs results from the superior material properties of GaN,
drain voltage. The gate leakage current of the AlGaN/GaN
which makes them an attractive choice for high power and
HFETs is dominated by the presence of shallow traps in the
high frequency applications.1 The large band gap of GaN
surface layer of the device. The contrasting I-V characteris-
facilitates a large breakdown field and the superior thermal
tics of the gate leakage current of InAlN/GaN HFETs can be
conductivity, and high sheet charge density enable excep-
explained by considering the effect of deep traps in the space
tional high operating power density over the conventional
charge limited (SCL) current flow through the InAlN surface
GaAs and SiC devices.2 The ability to form heterojunction in
layer. In this paper, we present a physics based model con-
InN, AlN, and GaN offers different configurations of hetero-
sidering SCL current flow through the surface of the device
structures to be formed and allows design of the polarity of
in the presence of deep traps in the InAlN cap layer to dem-
the heterostructures, which determine the 2DEG densities.
onstrate the gate leakage mechanism in the InAlN/GaN
Of the various heterostructures, AlGaN/GaN configuration is
HFETs.
the most popular and AlGaN/GaN HFETs demonstrate out-
standing performances yielding in the highest output power
II. THEORY
(30 W/mm) of all solid state devices.3 But due to the lattice
mismatch of AlGaN and GaN, the AlGaN layer is under ten- In a typical GaN HFET, the gate leakage current flows
sile strain which degrades the reliability of the AlGaN/GaN through two paths: the surface of the device, and through the
devices. By replacing AlGaN with InAlN, the device perform- layer under the gate to the 2DEG channel.9 Due to the pres-
ance and reliability can be improved as InAlN can be grown ence of deep traps (e.g., Ea  2.4 eV) in the InAlN cap layer,
lattice matched to GaN.4 InAlN/GaN HFETs also display a the trap assisted tunneling (TAT)10 rate from the gate to the
higher chemical and thermal stability than their AlGaN/GaN 2DEG channel is reduced and the SCL current flowing
counterparts. Due to the high value of spontaneous polariza- through the InAlN surface layer plays the dominant role in
tion in InAlN, the 2DEG sheet charge density is much higher the gate leakage current in InAlN/GaN HFETs. For the for-
for the InAlN/GaN devices,5 which makes it possible to mulation of the gate leakage model, the undoped InAlN layer
implement a thinner barrier to improve the gate control of the is considered as an insulator and the SCL current flow is
channel current. Lattice matched N-polar InAlN/GaN devices evaluated through the insulator in the presence of traps. In a
have attracted sufficient interest due their potential of realizing typical insulator, there exist both deep and shallow traps.
strong back barrier, low-resistivity Ohmic contact, and Traps having its energy level below the Fermi level are
improved performance and scalability.6,7 High aspect ratio called deep traps and those having energy level above the
and improved electron confinement mitigate the short channel Fermi level are called shallow traps. In a trap free insulator,
effects in N-polar GaN HFETs.8 all injected electrons remain free, i.e., in the conduction band
Although the lattice matched N-polar InAlN/GaN heter- and all contribute to the space charge and current conduc-
ojunction improves the performance and stability of the de- tion. The presence of traps in an insulator will impede the
vice, the gate leakage current of the InAlN/GaN HFETs is current flow at lower injection levels, since those traps ini-
comparable to or higher than their AlGaN/GaN counterparts. tially empty, will capture and thereby immobilized most of
The I-V profile of the gate leakage current of InAlN/GaN the injected charge. However, the amount of excess charge
HFETs is different from that of AlGaN/GaN HFETs, which that can be supported by the insulator at an applied voltage is

0021-8979/2014/116(16)/164508/6/$30.00 116, 164508-1 C 2014 AIP Publishing LLC

V

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 164508-2 Goswami, Trew, and Bilbro J. Appl. Phys. 116, 164508 (2014)

FIG. 1. N-polar InAlN/GaN HFET with 20 Å InAlN cap layer. The back
barrier consists of AlN, InAlN and AlGaN layers.

the same whether the excess charges are free or trapped. The FIG. 3. TCAD simulation of the vertical electrical field (Ey) along a vertical
trapped charges will not contribute to the current flow but cutline at the drain side gate edge of an InAlN/GaN HFET for increasing
gate voltage.
will affect the background electric field.
The N-polar InAlN/GaN HFET is shown in Figure 1 and
the energy band profile of the device at the drain side gate the gate leakage current flow. The electric field along the
edge is shown in Figure 2. The device is grown on a sapphire vertical slab of the device is shown in Figure 3. Because of
heterosubstrate. The 2DEG is located at the interface of the the lattice matched InAlN and GaN layers, there is no addi-
GaN and AlN/InAlN layers. The 20 Å InAlN cap layer forms tional piezoelectric field across the interface due to the ab-
the surface of the device. The back-barrier is used to increase sence of tensile or compressive strain in the InAlN cap layer.
the 2DEG confinement. The cap layer is added to reduce the Figure 4 shows the TAT rate of electrons from the gate ver-
stress in the GaN layer. In high electric field, the stress sus the vertical electric field for shallow and deep trap levels.
increases in the GaN layer at the drain side gate edge result- It is observed from Figure 4 that the TAT rate is higher in
ing in the formation of electrically active defects which de- case of shallow traps (0.30 eV) than the deep traps
grade the reliability of the device.11,12 The cap layer (2.41 eV). The deep traps require higher magnitude of elec-
provides robustness and mechanical strengthening to the tric field to start conducting through the TAT mechanism
Schottky barrier and mitigates the formation of defects in than the shallow traps. The presence of shallow traps at the
GaN HEMTs.13 The gate leakage current in N-polar HEMTs surface of InAlN layer at the gate edge in the drain access
with AlGaN cap is found to be reduced since the Schottky region facilitates the high electron injection due to TAT
barrier height is much higher on AlGaN than on GaN.14 Due mechanism from the gate to the surface layer. For the formu-
to the barrier at the interface of InAlN_cap/GaN layers lation of the SCL current through the surface, the gate is con-
shown in Figure 2, the electrons tunneling from the gate to sidered an infinite reservoir of electrons and the current flow
the surface form a conducting path of the gate leakage cur- through the surface is conduction limited. The gate metal
rent through the surface of the device. The electrons tunnel- extends into the InAlN layer and the deep traps in the InAlN
ing from the gate to the 2DEG form the secondary path to

FIG. 4. Injected carriers concentration at the surface (blue curve), and at the
2DEG channel (red curve) by the TAT process from the gate electrode ver-
FIG. 2. TCAD simulation of the energy band profile along a vertical cutline sus the electric field across the tunnel barrier. 2.41 eV of trap level in the
of an InAlN/GaN HFET in the drain access region. The electrons tunneling InAlN layer is considered for the TAT of gate electrons to the 2DEG and
from the gate accumulate at the 2DEG due to the band bending resulting 0.30 eV level of traps is considered for TAT from the gate electrode to the
from the polarization electric field. surface.

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 164508-3 Goswami, Trew, and Bilbro J. Appl. Phys. 116, 164508 (2014)

layer aids in the TAT of electrons from the gate vertically to

the InAlN layer into the 2DEG establishing a gate leakage
current path to the drain electrode.
Due to the presence of deep trap levels in the InAlN cap
layer, the TAT injection of electrons from the gate to the
2DEG is significantly reduced. The vertical electric field across
the InAlN cap layer is not sufficiently high to cause appreciable
carrier injection from the gate to the 2DEG through TAT
mechanism as confirmed from Figures 3 and 4. The tunneling
of electrons due to the conventional Fowler-Nordheim (FN)
tunneling mechanism is negligible compared to the TAT mech-
anism9 and is ignored in the formulation of the gate leakage
model. For the N-polar InAlN/GaN devices in which there is a
SiN layer between the gate metal and the InAlN cap layer, the
gate leakage I-V profile has the signature of the effects of shal- FIG. 5. Schematic of energy band diagram of the InAlN cap layer in the
low traps (present in the SiN layer) on the current conduction drain access region showing the four regions signifying the dominance of
and the gate leakage mechanism can be modeled using.9 the different charge carriers on the SCL current flow.
For the device shown in Figure 1, the injected electrons
from the gate accumulate in the InAlN cap layer and create a concentration of free carriers is equal to the thermal carrier
space charge. Most of the injected carriers will be captured by concentration, and the SCL current in this region is domi-
the deep traps in the InAlN cap layer and for gate-drain volt- nated by the thermal carriers. In the region to the left of x3,
age less than the trap filled limit voltage (VTFL),15 the surface the deep traps start filling, and the inception of the SCL cur-
current will be negligible. At Vgd ¼ VTFL, all the deep traps rent through the InAlN layer is affected by the shallow traps
in the drain access region are filled and the flow of the injected at level Et1. At plane x2, all the deep traps are filled as the
carriers in the InAlN conduction band is dominated by the gate-drain voltage exceeds the VTFL voltage. In this region,
shallow traps. The shallow traps cannot be completely filled at the injected carriers will dominate the current flow and the
room temperature.16 The equilibrium trap occupancy results square law dependence of the SCL current versus the voltage
from a balance between capture of electrons into the traps, is affected by the 1st level of shallow traps. At slightly
and their thermal re-emission into the conduction band. The higher voltage, the second shallow trap region, which
SCL current flowing through the InAlN cap layer establishes extends to the left of x1 where the flow of the SCL current is
the primary path for the gate leakage current between the gate affected by the shallow traps at level Et2, is observed.
and the drain electrodes. The current voltage relationship of The Poisson’s equation in region 1, where the current
the SCL current flowing through the InAlN cap layer is eval- flow is dominated by the 2nd level of shallow traps in the
uated by simultaneously solving the Poisson’s and current InAlN cap layer, is given by
density equations. Poisson’s equation in an insulator in the
presence of trapped electrons is given by dE e n
¼ ; (3)
dx e h2
dE e
¼ ððn  n0 Þ þ ðnt  nto ÞÞ; (1) where
dx e
where n ¼ concentration of free carriers, no ¼ concentration 1 gNt2
¼1þ (4)
of free carriers in thermal equilibrium, nt ¼ concentration of h2 N2
trapped electrons, and nto ¼ concentration of trapped elec-
trons in thermal equilibrium. and
Using the current density equation and after simplifica-  
ðEt2  Ec Þ
tion, we derive the following differential equation: N2 ¼ Nc exp : (5)
KT
dE J 1 e
 E  ðnt  nto  no Þ ¼ 0: (2) Nt2 is the trap density at level Et2, and g is the degeneracy
dx el e
factor (here it is assumed as 1).
We derive the exact solution to the above differential equa- Poisson’s equation in region 2 where the current flow is
tion in terms of the LambertW function.17 Although the solu- dominated by the 1st level of shallow traps in the InAlN cap
tion is too complicated for robust implementation in layer is given by
commercial software, the problem can be simplified by dE e n
¼ ; (6)
application of a regional approximation where the InAlN cap dx e h1
layer is divided into three regions on the basis of the domi-
where
nance of different charge carriers in the regions.
As shown in Figure 5, the injected free carrier concen- 1 gNt1
tration ni decreases monotonically from 1 at x ¼ 0. At low ¼1þ (7)
h1 N1
injection level, there will be a plane x3 where the and

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 164508-4 Goswami, Trew, and Bilbro J. Appl. Phys. 116, 164508 (2014)

 
ðEt1  Ec Þ solutions for all regions. For the first region, we observe that
N1 ¼ Nc exp : (8) the current is a function of the square of the voltage. In this
KT
region, the second level of shallow traps affects the SCL cur-
Nt1 is the trap density at level Et1. rent flow through the InAlN layer and the SCL current-
In region 3, the SCL current flow is dominated by the density voltage relationship is expressed as
deep traps in the InAlN cap layer and Poisson’s equation for
this region is given by 9 elh2 V 2
J¼ ; (12)
8 L3
dE e
¼ N (9) where l is the electron mobility at the surface and L is the
dx e
gate to drain spacing.
where In the second region, we observe similar square law
Nt current-voltage dependence as the first region. In this region,
N¼  : (10)
Fo  Et the first level of shallow traps dominates the SCL current
1 þ g exp flow through the surface layer and the SCL current-density
KT
voltage relationship is given by
Nt is the concentration of the deep traps at level Et.
The thermal carrier concentration dominates the current 9 elh1 V 2
flow in region 4 and Poisson’s equation is expressed as J¼ : (13)
8 L3
dE The VTFL is the cross-over voltage between the second and
¼ 0: (11)
dx the third region. In the third region, the deep traps start filling
Poisson’s equation is solved along with the current density up, and the flow of the electrons though the conduction band
equation for each region. Electric field continuity is enforced is affected by the first level of shallow traps. The current-
at the boundaries of the different regions to derive the density voltage relationship is given as

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
6q2 lN 2 h1 L  12q2 lN 2 L  36q4 l2 N 4 L2  24q4 l2 N 4 h1 L2 þ 18q3 l2 N 3 eh21 V  24q3 l2 N 3 eh1 V
J¼ : (14)
3eh21  4eh1

The current-voltage relationship in the fourth region is linear which are not captured by the deep traps accumulate in the
and is dominated by the thermal carriers in the InAlN layer conduction band of the InAlN cap layer and flow towards
and the SCL current-density voltage relationship is given as the drain electrode. The SCL conduction mechanism is
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi affected by the first level of shallow traps at the InAlN sur-
q2 lNno L  q4 l2 N 2 n2o L2  2q3 l2 Nn2o eV face. This region is called the TFL region and it approaches
J¼ : (15)
e the square law region at Vgd ¼ VTFL ¼ 8.09 V. In this
region, all the deep traps are filled and the SCL current is
dominated by the first level of shallow traps. The second
III. MODEL VERIFICATION level of shallow traps start dominating the SCL current
The model is verified by comparing the model results flow at Vgd ¼ 8.22 V. The extracted values of the trap level
against the gate leakage measurement data of a 1x150 and trap concentration is given in Table I. The model gives
micron N-polar InAlN/GaN HFET. The modeled and meas- the value of the extracted deep trap level in terms of Fo-Et.
ured gate leakage current densities versus the gate-drain The Fermi level of the undoped InAlN cap layer is
voltage are shown in Figure 6(a). Three distinctive regions assumed to be at the mid gap level. The total energy of
have been observed in the gate leakage I-V plot: an ohmic electrons used in the TAT formulation is taken as 0.2 eV
region; the TFL region; and a square law region. The (Ref. 10). The modeled and the measured gate leakage cur-
cross-over voltages, which separate the three regions, rent are plotted in log scale versus the gate-drain voltage
depend on the concentration of the traps, the depth of the shown in Figure 6(b). The gate leakage model prediction
trap level, the material properties and dimensions of the de- deviates from the measurement data for Vgd < 3.02 V. At
vice. For gate-drain voltage (Vgd) of 0–3.02 V, we observe lower voltages, when the flow of the electrons through the
an ohmic region due to the thermal carrier concentration in conduction band is limited, the gate leakage current flow
the InAlN layer. In this region, all the injected electrons due to the trap to trap hopping mechanism18 becomes sig-
from the gate electrode are captured by the deep traps. For nificant. In the current analysis, we have ignored trap to
Vgd > 3.02 V, the deep traps start filling up and the current trap hopping mechanism to keep the model simple and to
abruptly increases. The injected electrons from the gate obtain analytical solutions.

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 164508-5 Goswami, Trew, and Bilbro J. Appl. Phys. 116, 164508 (2014)

FIG. 6. (a) Modeled (red) versus measurement (blue) gate leakage current density for 1  150 l N-polar InAlN/GaN HFET with gate to drain spacing of 2 l. (b)
Modeled (red) versus measurement (blue) gate leakage current for 1  150 l N-polar InAlN/GaN HFET with gate-drain spacing of 2 l is plotted in log scale.

TABLE I. Gate leakage model parameters. 1

U. K. Mishra, P. Parikh, and Y. F. Wu, “AlGaN/GaN HEMTs—An over-
view of device operation and applications,” Proc. IEEE 90(6), 1022–1031
Values used to fit measurement (2002).
2
Parameters data for 150 l InAlN/GaN HFET R. J. Trew, “SiC and GaN transistors—Is there one winner for microwave
power applications?,” Proc. IEEE 90(6), 1032–1047 (2002).
3
Deep Trap level Et (eV) 2.41 Y. F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M.
Trap concentration at level Et (cm3) 1.207  1017 Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, “30-W/mm GaN
Shallow trap level Et2 (eV) 0.30 HEMTs by field plate optimization,” IEEE Electron Device Lett. 25(3),
117–119 (2004).
Trap concentration at level Et2 (cm3) 3  1012 4
J. Kuzmik, “InAlN/(In)GaN high electron mobility transistors: some
Shallow trap level Et1 (eV) 0.197 aspects of the quantum well heterostructure proposal,” Semicond. Sci.
Trap concentration at level Et1 (cm3) 6.42  1012 Technol. 17, 540–544 (2002).
Low field mobility (cm2/V.s) 450 5
O. Ambacher, J. Majewski, C. Miskys, A. Link, M. Hermann, M.
Electron energy (eV) 0.2 Eickhoff, M. Stutzmann, F. Bernardini, V. Fiorentini, V. Tilak, B. Schaff,
and L. F. Eastman, “Pyroelectric properties of Al(In)GaN/GaN hetero- and
quantum well structures,” J. Phys.: Condens. Matter 14, 3399–3434 (2002).
6
Nidhi, S. Dasgupta, J. Lu, J. S. Speck, and U. K. Mishra, “Self-aligned N-
IV. CONCLUSION polar GaN/InAlN MIS-HEMTs with record extrinsic transconductance of
1105 mS/mm,” IEEE Electron Device Lett. 33(6), 794–796 (2012).
A physics based model of the gate leakage current in N- 7
S. Dasgupta, Nidhi, S. Choi, F. Wu, J. S. Speck, and U. K. Mishra,
polar InAlN/GaN devices is demonstrated by considering the “Growth, structural, and electrical characterizations of N-Polar InAlN by
SCL current flow through the InAlN surface layer in the plasma-assisted molecular beam epitaxy,” Appl. Phys. Express 4, 045502
(2011).
presence of deep traps. It is established from the model that 8
M. H. Wong, S. Keller, Nidhi, S. Dasgupta, D. J. Denninghoff, S. Kolluri,
in the InAlN/GaN HFETs, the gate leakage current flowing D. F. Brown, J. Lu, N. A. Fichtenbaum, E. Ahmadi, U. Singisetti, A.
through the surface layer dominates the current flow through Chini, S. Rajan, S. P. DenBaars, J. S. Speck, and U. K. Mishra, “N-polar
the 2DEG channel. In the I-V profile of the gate leakage for GaN epitaxy and high electron mobility transistors,” Semicond. Sci.
Technol. 28, 074009 (2013).
InAlN/GaN HFETs, the leakage current abruptly increases 9
A. Goswami, R. J. Trew, and G. L. Bilbro, “Modeling of gate leakage cur-
when the deep traps in the InAlN cap layer start to fill by rent in AlGaN/GaN HFETs,” IEEE Trans. Electron Devices 61(4),
electrons tunneling from the gate electrode. The shallow 10
1014–1021 (2014).
traps dominate the SCL current flow when the gate-drain S. Fleischer, P. T. Lai, and Y. C. Cheng, “Simplified closed-form trap-
assisted tunneling model applied to nitrided oxide dielectric capacitors,”
voltage exceeds the trap filled limit voltage. The model is J. Appl. Phys. 72, 5711 (1992).
physical and requires minimum fitting parameters. 11
J. A. del Alamo and J. Joh, “GaN HEMT reliability,” Microelectron.
Reliab. 49, 1200–1206 (2009).
12
ACKNOWLEDGMENTS J. Joh, L. Xia, and J. A. del Alamo, “Gate current degradation mechanisms
of GaN high electron mobility transistors,” IEEE IEDM tech. digest 2007,
The author would like to thank the researchers Matthew 385–388.
13
P. Ivo, A. Glowacki, R. Pazirandeh, E. Bahat-Treidel, R. Lossy, J. W€ urfl,
Guidry, Jing Lu, and Xun Zheng of Dr. Umesh K. Mishra’s C. Boit, and G. Tr€ankle, “Influence of GaN cap on robustness of AlGaN/
research group at UC Santa Barbara, Santa Barbara, CA for GaN HEMTs,” in IEEE CFP09RPS-CDR 47th Annual International
providing us the gate leakage measurement data. Reliability Physics Symposium, Montreal (2009).

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S. Rajan, A. Chini, M. H. Wong, J. S. Speck, and U. K. Mishra, “N-polar trapped at high field,” Solid-Smre Ekctronics 38(11), 1887–1891
GaN/AlGaN/GaN high electron mobility transistors,” J. Appl. Phys. 102, (1995).
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044501 (2007). A. Goswami, R. J. Trew, and G. L. Bilbro, “Physics based modeling of
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M. A. Lampert, “Simplified theory of space-charge-limited currents in an gate leakage current due to traps in AlGaN/GaN HFETs,” Solid-State
insulator with traps,” Phys. Rev. 103(6), 1648–1656 (1956). Electron. 80, 23–27 (2013).
16 18
B. L. Yang, H. Wong, and Y. C. Cheng, “Study of shallow bulk W. Kuang, “TCAD simulation and modeling of AlGaN/GaN HFETs,”
traps in thin nitride oxide films by thermal re-emission of electrons Ph.D. dissertation (North Carolina State University, 2008).

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