GaN-based lateral and vertical devices:

physical mechanisms limiting stability and reliability

Gaudenzio Meneghesso, Matteo Meneghini, Carlo De Santi, Enrico Zanoni
University of Padova, Department of Information Engineering, via Gradenigo 6/B., 35131 Padova, Italy

increase in gate leakage (Figure 1, left). To

Abstract understand the physical origin of failures, we
GaN-based devices are creating a technological identified the location of the failed region by
revolution and are expected to replace silicon electroluminescence and cross-sectioned the devices
transistors for the development of high-efficiency by TEM (Figure 1, right). The results clearly
power converters. For this reason, a significant indicated that failure occurs in the silicon nitride
research effort is being spent towards the fabrication between the field plate edge and the drain terminal,
of high-performance and high-reliability GaN which is a high field region [3]. A short-circuit path
transistors. Despite this, the reliability of GaN is created between the 2DEG and the gate-head,
HEMTs is still limited by a number of factors, that leading to a sudden increase in gate leakage. The
can significantly reduce device lifetime and lead to results indicated that there is a strong correlation
early failures. This paper presents an overview of the between device lifetime and potential/field
physical processes responsible for the failure of GaN distribution; an accurate optimization of the electric
transistors for power electronics, with focus on: (i) field is a necessary step for achieving high reliability
degradation under off-state conditions; (ii) transistors. The conclusions of this work were used to
degradation in semi-on conditions; (iii) degradation propose an improved approach for the development
in the on-state (positive gate bias). The results of reliable devices, i.e. the use of an additional graded
presented here help understanding the most common SiN passivation under the gate head. The role of SiN
degradation modes of GaN devices and can be used properties was explored also in [4].
to improve manufacturing technology.
Introduction
GaN-based devices represent an excellent
opportunity for the development of the next-
generation power converters. Lateral GaN-on-Si
devices with a blocking voltage of 600-650 V are
already commercially available, and vertical GaN-
on-GaN diodes and transistors are being studied to
reach breakdown voltages above 1 kV.
GaN HEMTs are expected to be operated at much
harder conditions compared to the silicon counterpart,
thanks to the unique characteristics of GaN as a
semiconductor. The temperatures (>200 °C) and
fields (>3 MV/cm) are significantly higher than in
silicon transistors, and this represents a potential
issue for reliability. For this reason, studying the
Figure 1: (left) Constant voltage stress performed on a representative
reliability-limiting mechanisms of GaN devices is a device at gate voltage = –5 V, drain voltage = 600 V, and source and
necessary step to ensure a rapid market penetration. substrate grounded; (top right) Emission microscopy evaluated during
stress with VGS=–5V and VDS= 600 V; (bottom right) TEM performed
This paper summarizes our most recent results in the on a cross section corresponding to the hot spot. © [2017] IEEE.
field, by discussing the most relevant degradation Reprinted, with permission, from [1]
mechanism detected under off-state, semi-on state
and on-state stress. When devices are submitted to off-state bias, a
second process may take place: in fact, the large
Degradation processes under off-state stress drain-substrate voltage difference may lead to a
When lateral GaN devices are submitted to off-state significant depletion of the buffer, with consequent
stress, a high field builds up in the gate-drain access increase in the vertical electric field. Recently, we
region and across the buffer layer. Both lateral and demonstrated the exposure to high drain-substrate
vertical field can favor a time-dependent degradation bias can lead to a time-dependent vertical breakdown
of the devices, thus leading to early failures. of GaN-on-Si HEMTs. We carried out a set of step-
We discuss here two relevant and representative case stress experiments, by increasing the voltage applied
studies. In the first case, lateral GaN HEMTs were on the drain while keeping the substrate grounded.
submitted to stress at high constant voltage (600 V) With increasing stress voltage, we measured a
in the off-state [1], [2]. During stress time, the onset substantial increase in the noise superimposed to gate
of a time-dependent failure was observed. Both soft- leakage current, followed by a catastrophic failure of
and hard-failures were observed, leading to an the samples [5]. Further measurements carried out
978-1-5386-6508-4/19/$31.00 ©2019 IEEE 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
under constant vertical bias indicated that: (i) during overestimates the trapping effects, while on the other
a constant voltage stress, vertical leakage is initially hand it permits an accurate description of the pulsed
stable, then it becomes noisy, indicating the and electroluminescence characteristics of the
generation of defects. (ii) For longer times, failure is samples. To evaluate the impact of hot-electrons on
reached, leading to the shortening of vertical stack. device performance, dynamic-Ron was evaluated as
(iii) time-to-failure (TTF) is Weibull-distributed. a function of the overlapping between gate and drain
Degradation was interpreted as follows: when a high waveforms, by moving from a positive drain-gate
vertical bias is applied to the devices, a small leakage delay (DGD, soft switching) to a negative drain-gate
current flows through bulk conduction and delay (hard switching). The results, summarized in
dislocation-assisted processes. The buffer is deeply Figure 3, indicate that hard switching can induce a
depleted, and behaves as a leaky insulator, showing a measurable increase in dynamic-Ron. The magnitude
time-dependent breakdown process. Dislocations of this increase depends on the drain voltage applied
may locally accelerate breakdown, due to the higher and on the duration of the overlapping between the
vertical leakage. This process can limit the time-to- drain and gate waveforms (Figure 3 (a)).
failure of the devices, but is not a major limiting Electroluminescence was used as a tool to prove the
factor. We recently demonstrated [5] that 200 V role of hot-electrons in the analyzed mechanism
devices can have a 20 years lifetime at 560 V with (Figure 3 (b)), and the following results were
1 % failure rate. TTF can be further improved by obtained: (i) there is a strong correlation between the
reducing the density of defects in the vertical stack, increase in dynamic-Ron and the EL signal measured
and by optimizing the electric field profile. during hard switching; (ii) at high temperatures, the
effect of hot-electrons becomes less prevalent, due to
an increased scattering. Strategies for minimizing
hot-electrons effects include the minimization of the
electric field (at device level) and the optimization of
the switching characteristics (at system level).

Figure 2: (left) Drain current monitored during a constant voltage

stress (VD=800 V); (right) TTF dependence on the drain voltage
applied at ambient temperature of 30 °C and 150 °C. Each point
represents the Weibull scale factor with a confidence level of 99%. ©
[2017] IEEE. Reprinted, with permission, from [5]

Degradation processes under semi-on state stress

Another critical operation regime is reached when the
transistors are operated in semi-on stress conditions
[6]. This is not a permanent operation regime, but a Figure 3: (left) ON-resistance dynamic variation plotted as a
function of the drain quiescent bias point (VDSQ) for several DGD
condition which is crossed when the device is values. The dynamic change of the ON-resistance has a non-
switched. For instance, in a boost converter, when the monotonic trend with the VDSQ, showing a maximum for VDSQ = 300
V. (right) Correlation between the increase in the EL signal and the
device goes from off-to on-state, the drain current increase in the dynamic ON-resistance with a low DGD value applied.
starts increasing before the drain voltage has dropped © [2017] IEEE. Reprinted, with permission, from [8]
to nearly 0 V (linear regime). As a consequence, there
is a short time-frame (few tens of ns) during which Degradation processes under on-state stress
In on-state conditions, GaN devices are exposed to
high current and high voltage are both present. This low drain voltage; however, normally-off transistors
may enhance hot electron effects, resulting in must operate with a positive gate bias when they are
degradation and trapping processes that are not on, and this may result in additional degradation
present under off-state conditions. Several processes. Recently, several research groups studied
approaches can be used to study the performance and the degradation of GaN power devices submitted to
the reliability of GaN transistors under hard positive gate stress, to assess the stability of the gate
switching. Two interesting approaches are the use of stack [9]–[15]. The main findings can be summarized
an inductive load, as proposed by Tanaka et al. in [7], as follows: (i) insulated gate GaN transistors may
and the tuning of gate and drain square-waves in suffer from dielectric-related time-dependent failures
order to ensure a non-negligible overlap between the [16][17]. In addition, time-to-failure is Weibull-
two [7]. distributed [17][16]. (ii) transistors with p-GaN gate
may suffer from a field-driven breakdown of the
With reference to this second case, on one hand it

2019 Electron Devices Technology and Manufacturing Conference (EDTM)

metal/p-GaN Schottky junction, that was observed International Cooperation, "Direzione Generale per
under pulsed TLP testing; the same devices may la Promozione del Sistema Paese", through the Italy-
suffer also from a time-dependent breakdown, when Japan bilateral project "MAGYGAN"; 3) by the
submitted to long-term constant voltage stress [18]. project InRel-NPower (Innovative Reliable Nitride
Results suggest the creation of a percolation path in based Power Devices and Applications). This project
the AlGaN barrier, as indicated by recent studies [11].
A significant improvement in lifetime was achieved has received funding from the European Union’s
through optimization of the barrier parameters [11]. Horizon 2020 research and innovation programme
(iii) vertical GaN devices based on MOS structure under grant agreement No 720527.
may suffer from trapping and failure processes [19],
[20]. Failures have been found to occur above 7 V for References
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2019 Electron Devices Technology and Manufacturing Conference (EDTM)