MITSUBISHI < STD.
LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
GENERAL DESCRIPTION
The M62320P/FP is a CMOS 8-bit I/O expander which has
serial to parallel and parallel to serial data converting
PIN CONFIGURATION(TOP VIEW)
functions.
It can communicate with a microcontroller via few wiring
2
thanks to the adoption of the two-line I C BUS.
SO 1 16 CS0
Parallel data I/O terminal can be set to input or output
mode alternatively in individual bits. SCL 2 15 CS1
M62320P,FP
Maximum 8 ICs can be connected to a bus by using three SDA 3 14 CS2
chip-select pins, so that it is possible to handle up to 64 bits D0 4 13 VDD
data. D1 5 12 D7
D2 6 11 D6
FEATURES
D3 7 10 D5
• Simple two-line (SCL and SDA) communication with a
GND 8 9 D4
microcontroller.
• 8-bit data conversion between serial and parallel by
I2 C BUS.
• Built-in power-on reset. Outline 16P4(P)
16P2N(FP)
APPLICATION
I/O port expansion for a microcontroller.
Data conversion between serial and parallel in
microcontroller peripherals.
BLOCK DIAGRAM
CS0 CS1 CS2
16 15 14
CHIP-SELECT
SCL 2 2
I C BUS
SDA 3
TRANSCEIVER SHIFT
1 SO
REGISTER
Output Data Input/Output
8 8 8
OUTPUT DATA I/O SETTING INPUT DATA
LATCH DATA LATCH LATCH
8 8 8
Input Data
VDD 13 POWER-ON
RESET
Å@
I/O PORT
GND 8
12 11 10 9 7 6 5 4
D7 D6 D5 D4 D3 D2 D1 D0
2/20,1998(rev) ( 1 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
PIN DESCRIPTION
Pin No. Symbol I/O Function
2 SCL Input Serial clock input
Input/
3 SDA Serial data input/output
Output
1 SO Output Serial data output
16 CS0
15 CS1 Input Chip select data input
14 CS2
4 D0
5 D1
6 D2
7 D3 Input/
Parallel data input/output
9 D4 Output
10 D5
11 D6
12 D7
13 VDD Power supply
8 GND GND
2/20,1998(rev) ( 2 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Ratings Unit
VDD Supply voltage –0.3 to 7.0 V
VI Input voltage –0.3 to VDD+0.3 V
VO Output voltage –0.3 to VDD+0.3 V
IOH Output current "Low" D0 to D7 - 5 to 0 mA
IOL Output current "High" D0 to D7 0 to 30 mA
Pd Power dissipation Ta = 25°C 1220(P) / 980(FP) mW
Topr Operating temperature -20 to 85 °C
Tstg Storage temperature -40 to 125 °C
RECOMMENDED OPERATING CONDITIONS
• Supply voltage………VDD=5V±10%
• Input high voltage……VIH=0.8VDD to VDD
• Input low voltage………VIL=0 to 0.2VDD
ELECTRICAL CHARACTERISTICS (VDD=5V ±10%, GND=0V,Ta=20 to 85°C, unless otherwise noted)
Limits
Symbol Parameter Conditions Unit
Min Typ Max
VIH = VDD,VIL = GND, 0.5 mA
0.05
IDD Circuit current fSCL = 400kHZ
VIH = VDD,VIL = GND, 0.1 1.0 µA
fSCL = stop
IILK Input leak current -10 10 µA
VIH Input high voltage 0.8VDD V
VIL Input low voltage 0.2VDD V
VOH Output high voltage IOH = -1mA VDD-0.4 V
VOL Output low voltage IOL = 5mA 0.4 V
VOL = 0.4V 5 10 mA
IOL Output current "Low"
VOL = 1.0V 15 25 mA
2/20,1998(rev) ( 3 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
2
I C BUS CHARACTERISTICS
Limits
Symbol Unit
Parameter Min. Max.
fSCL SCL clock frequency 0 100 KHz
tBUF Free time: the bus must be free before a new transmission can start 4.7 - µs
Hold time START Condition. After this period,the first clock pulse 4.0 - µs
tHD:STA is generated.
tLOW LOW period of the clock 4.7 - µs
tHIGH HIGh period of the clock 4.0 - µs
Set-up time for START condition (Only relevant for a repeated 4.7 - µs
tSU:STA START condition)
tHD:DAT Data Hold time 0 - µs
tSU:DAT Data Set-up time 250 - ns
tR Rise time of SDA and SCL signals - 1000 ns
tF Fall time of SDA and SCL signals - 300 ns
tSU:STO Set-up time for STOP condition 4.0 - µs
• Note that a transmitter must internally provide at least a hold time to bridge the undefined region
(max.300 ns) of the falling edge of SCL.
TIMING CHART
tR, tF
tBUF
VIH
SDA
VIL
tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO
VIH
SCL
VIL
tLOW
tHIGH
START START STOP START
2/20,1998(rev) ( 4 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
FUNCTIONAL BLOCKS
I 2 C BUS interface
The I 2 C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection
by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulses, dedicated to each data latch
are generated.
Data Latch
This IC has 3 types of data latch : the I/O setting data latch, the input data latch and the output data latch
and each latch is controlled by the I2 C BUS interface.
• I/O setting data latch
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next
byte after receiving the slave address byte in the write mode from the master. In case this latch is set to
high, the data is transferred from the I2 C BUS interface to the parallel data terminals. In the opposite
transmission : from the parallel data terminals to the I2 C BUS, it is set to low.
• Output data latch
In the write mode, the data from the I2 C BUS to the parallel data terminals is latched. When the master
transmits output data after a setting in write mode, the output data is taken into the latches.
• Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is
taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock . The
latched data is output to the master through the sift resistor. On the output terminal assigned by the I /
O setting latch, the input data latch takes the state of the output terminal.
Parallel input / output port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and
is able to accept a input. In another case I/O setting latch is set to high (output mode), each parallel
terminal outputs a data according to the state of the output data latch.
Power on reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become
hi-impedance (input mode).
2/20,1998(rev) ( 5 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
DIGITAL DATA FORMAT
1. Write mode : I2 C BUS data input to Parallel data output
First Last
8BIT
S SLAVE ADDRESS W A I/O SETTING A 8BIT DATA A 8BIT DATA A A P
DATA
2
2. Read mode :Parallel data input to I C BUS data output
First Last
8BIT
S SLAVE ADDRESS W A 8BIT DATA A 8BIT DATA A 8BIT DATA A DATA A P
Transmission from Master (MCU etc.) to Slave (M62320)
Transmission from Slave (M62320) to Master (MCU etc.)
• S : Start Condition
While SCL level is high, SDA line level should be changed from high to low.
• Slave address
• Chip select data
First Last
MSB LSB MSB LSB
0 1 1 1 A2 A1 A0 A2 A1 A0 CS2 CS1 CS0
0 0 0 L L L
0 0 1 L L H
Lower three bits (A0,A1,A2) are a programmable address.
This IC is accessed only when the lower 3 bits data of slave 0 1 0 L H L
address coincide with the data of CS0 to CS2. (refer to the
right table)
1 1 1 H H H
(L=Low,H=High)
• W: Write (SDA = LOW), R : Read (SDA = HIGH)
• A: Acknowledge bit
• I/O setting data (I/O setting of parallel data I/O terminals.)
First Last
MSB LSB
• Each bit data corresponds to the I/O state of
P7 P6 P5 P4 P3 P2 P1 P0 the parallel data terminals.
DATA INPUT from parallel data terminals = Low
DATA OUTPUT to parallel data terminals = High
• 8bit data
First Last
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
• P : Stop condition
While SCL level is high, SDA level should be changed from low to high.
2/20,1998(rev) ( 6 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
FUNCTIONAL DESCRIPTION
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to
the output state, the corresponding terminals should be set during the write mode. This setting is hold until a
next setting.
2
In the write mode, 8 bits data can be transmitted from the I C BUS interface to the parallel ports continually after
the slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I2 C BUS interface continually after
the slave address setting.
In the case of a changing between the write- and read-mode, the data must be transmitted again from the
starting condition.
• In a case of a data conversion from serial to parallel.
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
starting
condition slave address I/O setting byte stop condition
DATA DATA
SDA 0 1 1 1 A2 A1 A0 0 A P7 P6 P5 P4 P3 P2 P1 P0 A D17D16 D15 D14 D13D12 D11 D10 A D27D26 D25 D24 D23D22 D21 D20 A
SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Data output Data output
D0
to Hi-Z D1X D2X
D7
• In a case of a data conversion from parallel to serial.
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O
setting resistors are set to the input mode after power-on.)
Transmission from a master (MCU etc.)
start Transmission from a slave (M62320)
condition slave address I/O setting byte
SDA 0 1 1 1 A2 A1 A0 0 A P7 P6 P5 P4 P3 P2 P1 P0 A
SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
D0 to D7
output Hi-Z
start
condition slave address stop condition
DATA DATA DATA
SDA 0 1 1 1 A2 A1 A0 1 A D17D16 D15 D14 D13D12 D11 D10 A D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43D42 D41 D40 A
SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
D0 to D7
Input D1X D2X D3 X D4X
(example)
data latch data latch data latch
D0 to D7
Output
Hi-Z
2/20,1998(rev) ( 7 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
• In case the I/O setting is different between each terminals.
An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,
respectively.
start condition stop condition
slave address I / O setting DATA DATA
SDA 0 1 1 1 A2 A1 A0 0 A P7 P6 P5 P4 P3 P2 P1 P0 A D17 D16 D15 D14 D13D12 D11 D10 A D27 D26 D25 D24 D23D22 D21 D20 A
SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Data output Data output
D0 to D3 Hi-Z D1X D2X
D4 to D7 Hi-Z
start condition stop condition
slave address DATA DATA DATA
SDA 0 1 1 1 A2 A1 A0 1 A D17 D16 D15 D14 D13D12 D11 D10 A D37 D36 D35 D34 D33D32 D31 D30 A D47D46 D45 D44 D43D42 D41 D40 A
SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
D0 to D3
D4 to D7
D1X D2X D3X D4X
(instance)
data latch data latch data latch
D4 to D7
output Hi-Z
• Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are
output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data
transmission.
The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data
setting.
• Read mode
The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the
terminal assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
2/20,1998(rev) ( 8 / 9 )
MITSUBISHI ELECTRIC
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
TYPICAL APPLICATION
10µF
13
VDD
D0 4
14 CS2
D1 5
Chip select data 15 CS1 D2 6
D3 7 Parallel input /
16 CS0
D4 9 output terminal
D5 10
D6 11
2 SCL
MCU D7 12
3 SDA
SO 1 Serial data output
GND
10
PRECAUTION FOR USE
2
• Purchase of MITSUBISHI ELECTRIC CORPORATION'S I C components conveys a
license under the Philips I2C Patent Rights to use these components an I2C system,
provided that the system conforms to I2 C Standard Specification as defined by Philips.
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may occur
with them. Trouble with semiconductors may lead to personal injury,fire or property
damage. Remember to give due consideration to safety when making your circuit design,
in order to prevent fires from spreading, redundancy, malfunction or other mishap.
2/20,1998(rev) ( 9 / 9 )
MITSUBISHI ELECTRIC
