A
Project Report
ON
Implementation of I2C using Verilog
1
Content
1. Introduction ___________________________________________________3
2. Application____________________________________________________3
3. Flowchart_____________________________________________________3
4. Working Principle______________________________________________4
5. Advantages & imitations_________________________________________4
6. Verilog Code
• Master code _________________________________________4
• Slave code __________________________________________6
7. Test bench
• Master code_________________________________________7
• Slave code__________________________________________8
8. RTL schematic _______________________________________________9
9. Results and Observation ________________________________________9
10. Refrences___________________________________________________10
2
INTRODUCTION
I2C stands for Inter-Integrated Circuit. It is a bus interface connection protocol incorporated
into devices for serial communication. It was originally designed by Philips Semiconductor in
1982. The I2C bus communication protocol is a two-wire interface (TWI) which uses only
two signal lines i.e. serial data (SDA) and serial clock (SCL) to establish synchronous serial
communication between a master and a single or multiple slave device[1][2][4].
Working of I2C Communication Protocol :
It uses only 2 bi-directional open-drain lines for data communication called SDA and SCL.
Both these lines are pulled high.
Serial Data (SDA) – Transfer of data takes place through this pin.
Serial Clock (SCL) – It carries the clock signal.
I2C operates in 2 modes –
• Master mode
• Slave mode
Each data bit transferred on SDA line is synchronized by a high to the low pulse of each
clock on the SCL line.
According to I2C protocols, the data line can not change when the clock line is high, it can
change only when the clock line is low. The 2 lines are open drain, hence a pull-up resistor is
required so that the lines are high since the devices on the I2C bus are active low. The data is
transmitted in the form of packets which comprises 9 bits[4].
Applications
• It is used in internal chip to chip communication
• DLSEDS methodology for designing secure systems [5]
• C buses are mainly used in Lon technology of field equipment network[6]
• airborne or avionics applications as a communication media to communicate between
two nodes[7]
• Camera Control Interface (CCI) uses I2C core protocol , and TI2C will use only
necessary modules of I2C core for camera control commands communication[8]
Fig 1.1 Flow chart of Master
3
Working Principle
Start and Stop Conditions :
The start command represents a high-to-low transition on the serial data SDA line while the
serial clock SCL line is high and the stop command represents a lowto- high transition on
serial data SDA line while the serial
clock SCL line is high [1]
Fig 1.2 Start and Stop Condition
Read/Write Bit :The R/W bit represents direction of data transfer between the master and
slave device over the bus, if R/W =0 i.e active low, the master device transmits a byte of data
to the slave device if R/W =1 i.e. master device receives a byte of data from slave [1].
ACK/NACK Bit : After every data frame, follows an ACK/NACK bit. If the data frame is
received successfully then ACK bit is sent to the sender by the receiver.
DATA:I2C bus supports data transfer in terms of bytes only that is one byte comprised of 8-
bits on the serial data SDA line. This byte may either be a device address, register address,
data written to or read from slave device, here one data bit is transferred during each clock
pulse of SCL with MSB first. Any number of data bytes can be transferred from master to
slave between the start and stop command, only condition is that the data on the SDA line
must remain stable during the high phase of clock period, as changes in the SDA line when
the clock is high is interpreted as start or stop command [7].
Advantages :
• Can be configured in multi-master mode.
• Complexity is reduced because it uses only 2 bi-directional lines (unlike SPI
Communication).
• Cost-efficient.
• It uses ACK/NACK feature due to which it has improved error handling
capabilities.
Limitations :
• Slower speed.
• Half-duplex communication is used in the I2C communication protocol.
Verilog code OF I2C_MASTER :
module I2C_protocol1(clk,rst,sda,scl,i2c_clk
);
input wire clk,rst;
output reg sda,scl,i2c_clk;
parameter STATE_IDLE=0;
parameter STATE_START=1;
parameter STATE_ADDR=2;
parameter STATE_RW=3;
parameter STATE_WACK=4;
4
parameter STATE_DATA=5;
parameter STATE_STOP=6;
parameter STATE_WACK2=7;
parameter DELAY= 1000;
reg [6:0]addr;
reg[7:0]data;
reg [7:0]state;
reg[7:0]count;
reg [9:0] count_clk = 0;
initial i2c_clk=0;
//assign ready = ((state == STATE_IDLE)&&(rst==0))?1:0;
always@(posedge clk)
begin
if(count_clk==(DELAY/2)) begin
i2c_clk =~i2c_clk;
count_clk =0; end
else
count_clk =count_clk+1;
end
always@(negedge i2c_clk)
begin
if(rst==1)begin
scl<=1; end
else if((state==STATE_IDLE)||(state==STATE_START)||(state==STATE_STOP))
begin
scl<=1; end
else
scl<=~scl;
end
always@(posedge i2c_clk)
begin
if(rst==1)begin
state<=0;
sda<=1;
count<=8'd0;
addr <= 7'h50;
data <= 8'haa; // start<=1;
end
else begin
case(state)
STATE_IDLE: begin
Sda <=1;
state<=STATE_START; end
STATE_START: begin
state<=STATE_ADDR;
sda <=0;
count<=6; end
STATE_ADDR: begin
sda<=addr[count];
5
if(count==0)
state<=STATE_RW;
else if(scl)
count<=count-1;end
STATE_RW: begin
sda<=1;
state<=STATE_WACK; end
STATE_WACK: begin
count<=7;
state<=STATE_DATA;
end
STATE_DATA: begin
sda<=data[count];
if(count==0)
state<=STATE_WACK2;
else if(scl)
count<=count-1;
end
STATE_WACK2: begin
state<=STATE_STOP;
end
STATE_STOP: begin
sda<=1;
state<=STATE_IDLE;
end
default: begin sda<=1;
state<=STATE_IDLE; end
endcase
end end
endmodule
CODE OF I2C_SLAVE
module i2c_slave_code(sda,i2c_clk,ack,nack,out );
input sda;
input i2c_clk;
reg [6:0]address;
reg [7:0]slave_data;
reg [6:0]addr_comp;
integer i=0;
integer c=0;
output reg ack;
output reg nack;
output reg out;
always@(posedge i2c_clk)
begin
ack<=0;
address<= 7'b0110111;
slave_data<=8'b00110010;
if(c<7)
6
addr_comp[c]<=sda;
c<=c+1;
if(addr_comp==address && sda ==1)
begin
if(i==0)
begin
ack<=1; end
if(i<8)
begin
slave_data[i]<=(~sda);
end
i<=i+1;
if(i==8)
begin
c<=0;
i<=0;
ack<=1;
end
end
else if(addr_comp==address && sda ==0)
begin
if(i==0)
begin
ack<=1; end
if(i<8)
begin
out<= (~slave_data[i]);
end
i<=i+1;
if(i==8)
begin c<=0;
nack<=1;
#100 nack<=0;
end end
else
begin
ack<=0;
end end
endmodule
TEST BENCH OF MASTER:
module I2C_MASTER_tb;
reg clk;
reg rst;
wire sda;
7
wire scl;
wire i2c_clk;
I2C_protocol1 uut (.clk(clk), .rst(rst), .sda(sda), .i2c_clk(i2c_clk), .scl(scl));
initial begin
clk = 0;
forever begin
clk= #5 ~clk;
end end
initial begin
rst = 1;
#10000; rst=0;
#6000000;
$finish;
end
endmodule
Test bench for I2c_slave:
module slave_code_tb;
reg i2c_clk;
wire ack;
wire nack;
wire out;
reg sda;
i2c_slave_code uut ( .sda(sda), .i2c_clk(i2c_clk), .ack(ack), .nack(nack), .out(out)
);
always #50 i2c_clk = ~ i2c_clk;
initial begin
i2c_clk = 1;
sda = 1;
#100; sda=1;
#100; sda=1;
#100; sda=0;
#100; sda=1;
#100; sda=1;
#100; sda=0;
#100; sda=0;
#10000000;
$finish;
end
endmodule
8
RTL schematic
(a) I2c_Master (b) RTL schematic of I2c_slave
Fig 1.3 RTL schematic of (a) I2c_Master (b) I2c_slave
Result and Observation:
I2c master and slave is designed with behavioural modelling technique and test code is
written for that RTL schematic for master and slave respectively .
Fig 1.4 I2C_SLAVE
Fig 1.5 I2C_MASTER
The functionality of the I2C protocol is verified. The code coverage and waveforms are
shown in the output section. End to end encryption and decryption has been performed for the
I2C master and slave for secure transfer of communicating data. The functionality of the
master and slave I2C protocol is verified.
9
Refrences
1. P. Bagdalkar and L. Ali, "Interfacing of light sensor with FPGA using I2C bus," 2020 6th
International Conference on Advanced Computing and Communication Systems (ICACCS),
2020, pp. 843-846, doi: 10.1109/ICACCS48705.2020.9074372.
2. R. S. S. Kumari and C. Gayathri, "Interfacing of MEMS motion sensor with FPGA using
I2C protocol," 2017 International Conference on Innovations in Information, Embedded and
Communication Systems (ICIIECS), 2017, pp. 1-5, doi: 10.1109/ICIIECS.2017.8275932.
3.https://www.ti.com/lit/an/slva704/slva704.pdf?ts=1636432584783&ref_url=https%253A%
252F%252Fwww.google.com%252F
4. https://www.geeksforgeeks.org/i2c-communication-
otocol/#:~:text=I2C%20stands%20for%20Inter%2DIntegrated,Two%20Wired%20Interface(
TWI).
5. D. Levshun, A. Chechulin and I. Kotenko, "A technique for design of secure data transfer
environment: Application for I2C protocol," 2018 IEEE Industrial Cyber-Physical Systems
(ICPS), 2018, pp. 789-794, doi: 10.1109/ICPHYS.2018.8390807.
6 .X. Lijun, S. Wei and L. Ying, "Combination Design of I2C and Lon Buses Based on
Bridge Mode," 2009 Pacific-Asia Conference on Circuits, Communications and Systems,
2009, pp. 277-280, doi: 10.1109/PACCS.2009.101.
7 .K. B. Bharath, K. V. Kumaraswamy and R. K. Swamy, "Design of arbitrated I2C protocol
with DO-254 compliance," 2016 International Conference on Emerging Technological
Trends (ICETT), 2016, pp. 1-5, doi: 10.1109/ICETT.2016.7873672.
8 .U. K. Malviya, A. swain and G. Kumar, "Tiny I2C Protocol for Camera Command
Exchange in CSI-2: A Review," 2020 International Conference on Inventive Computation
Technologies (ICICT), 2020, pp. 149-154, doi: 10.1109/ICICT48043.2020.9112536.
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