AUDISANKARA COLLEGE OF ENGINEERING & TECHNOLOGY

(AUTONOMOUS)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(23EC508)
Analog &Digital IC Applications Lab
LABORATORY OBSERVATION

NAME: _________________________________________________________________

ROLL NUMBER: ________________________________________________________

CLASS: _________________________________________________________________

YEAR/SEM: _____________________________________________________________

BRANCH: _______________________________________________________________
Program Educational Objectives (PEO's)

PEO1: Graduates will continue to demonstrate their competency and succeed in the core and allied areas
of Electronics & Communication Engineering or their chosen field of interest
PEO2: Graduates advance their education or professional practice that prepares them for a best in class of
entrepreneur in the diverse areas

PEO3: Graduates build leadership qualities and be an effective communicator to work in multi-disciplinary
areas promote and practice ethical values

Program Outcomes (PO's):

PO1: Engineering knowledge: Engineering Knowledge: Apply knowledge of mathematics, natural science,
computing, engineering fundamentals and an engineering specialization as specified in WK1 to WK4
respectively to develop to the solution of complex engineering problems

PO2: Problem Analysis: Identify, formulate, review research literature and analyze complex engineering
problems reaching substantiated conclusions with consideration for sustainable development. (WK1 to
WK4)

PO3:Design/Development of Solutions: Design creative solutions for complex engineering problems and
design/develop systems/components/processes to meet identified needs with consideration for the public
health and safety, whole-life cost, net zero carbon, culture, society and environment as required. (WK5)

PO4: Conduct Investigations of Complex Problems: Conduct investigations of complex engineering

problems using research-based knowledge including design of experiments, modelling, analysis &
interpretation of data to provide valid conclusions. (WK8)

PO5: Engineering Tool Usage: Create, select and apply appropriate techniques, resources and modern
engineering & IT tools, including prediction and modelling recognizing their limitations to solve complex
engineering problems. (WK2 and WK6)

PO6: The Engineer and The World: Analyze and evaluate societal and environmental aspects while solving
complex engineering problems for its impact on sustainability with reference to economy, health, safety,
legal framework, culture and environment. (WK1, WK5, and WK7)

PO7: Ethics: Apply ethical principles and commit to professional ethics, human values, diversity and
inclusion; adhere to national & international laws. (WK9)

PO8: Individual and Collaborative Team work: Function effectively as an individual, and as a member or
leader in diverse/multi-disciplinary teams
PO9: Communication: Communicate effectively and inclusively within the engineering community and
society at large, such as being able to comprehend and write effective reports and design documentation,
make effective presentations considering cultural, language, and learning differences

PO10: Project Management and Finance: Apply knowledge and understanding of engineering
management principles and economic decision-making and apply these to one’s own work, as a member
and leader in a team, and to manage projects and in multidisciplinary environments
PO11:Life-Long Learning: Recognize the need for and have the preparation and ability for i) independent
and life-long learning ii) adaptability to new and emerging technologies and iii) critical thinking in the
broadest context of technological change. (WK8)
Program Specific Outcomes (PSO's)

PSO1: Graduates will possess a comprehensive understanding of differential equations, linear algebra,
complex variables, and discrete mathematics, along with a solid foundation in communication theory and
practice

PSO2: Graduates will be skilled in applying probability, integral transforms, and circuit design concept,
with Handson experience in VLSI, embedded systems, and image processing, using modern computational
tools to solve engineering problems in Electronics and Communication Engineering

COURSE OBJECTIVES
 Design an Inverting and Non-inverting Amplifier using an Op Amp
 Analyse the Linear and Non-Linear Applications using IC 741.
 Design Astable and Monostable Multivibrator using timer ICs.
 Analyse the DAC and ADC converter.
 Design Counters and Registers using digital ICs.

COURSE OUTCOMES
After the completion of the course students will be able to
Course Course Outcome statements BTL
Outcomes

CO1 Design an Inverting and Non-inverting Amplifier using an Op Amp. L6

CO2 Analyse the Linear and Non-Linear Applications using IC 741. L4

CO3 Design Astable and Monostable Multivibrator using timer ICs. L6

CO4 Analyse the DAC and ADC converter. L4

CO5 Design Counters and Registers using digital ICs. L6

MAPPING OF COURSE OUTCOMES WITH PO’S AND PSO’S

Course Title PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PSO1 PSO2

CO1 3 3 3 3 3 3 3 3
CO2 3 3 3 3 3 3 3 3
CO3 3 3 3 3 3 3 3 3
CO4 3 3 3 3 3 3 3 3
CO5 3 3 3 3 3 3 3 3
 LABORATORY INSTRUCTIONS

1. While entering the Laboratory, the students should follow the dress code. (Wear shoes and
White apron, Female Students should tie their hair back).

2. The students should bring their observation book, record, calculator, necessary stationery items
and graph sheets if any for the lab classes without which the students will not be allowed for
doing the experiment.

3. All the Equipment and components should be handled with utmost care. Any breakage or
damage will be charged.

4. If any damage or breakage is noticed, it should be reported to the concerned in charge

immediately.

5. The theoretical calculations and the updated register values should be noted down in the
observation book and should be corrected by the lab in-charge on the same day of the
laboratory session.

6. Each experiment should be written in the record note book only after getting signature from the
lab in-charge in the observation notebook.

7. Record book must be submitted in the successive lab session after completion of experiment.
8. 100% attendance should be maintained for the laboratory classes.
Precautions.

1. Check the connections before giving the supply.

2. Observations should be done carefully
 INDEX
Page
S. No Date Name of the Experiment Signature
No
 1. INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIERS.

1(a) INVERTING AMPLIFIER

AIM:

To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required

THEORY:

The input signal V i is applied to the inverting input terminal through R 1 and the non-
inverting input terminal of the op-amp is grounded. The output voltage V o is fed back to the
inverting input terminal through the R f - R1 network, where R f is the feedback resistor. The
output voltage is given as,
Vo = - ACL Vi
0
Here the negative sign indicates that the output voltage is 180 out of phase with the input
signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
PIN DIAGRAM:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN:
Gain of an inverting amplifier Av = Vo/Vin = - Rf / Ri

The required gain = 10, That is

Av = - R f/ Ri = 10

Let Ri = 1KΩ, Then Rf = 10KΩ

Observations:
Vin = 1 Vpp
Vo=?
Gain, Av = Vo/Vin =?
Observed phase difference between the input and the output on the CRO =?
CALCULATION:

OBSERVATIONS:

Output
S.No Input

Amplitude
1.
( No. of div x Volts per
div )
Time period
2.
( No. of div x Time per
div )

MODEL GRAPH:

Vin

Vout
RESULT:

The design and testing of the inverting amplifier is done and the input and output waveforms
were drawn.

VIVA QUESTIONS:
1. What is an op-amp?
2. What is an inverting amplifier?
3. What is the difference between inverting and non inverting amplifier?
4. Define CMRR.
5. Write the equation for gain of an inverting amplifier.
 1(b) NON - INVERTING AMPLIFIER

AIM:

To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit
amplifies the signal without inverting the input signal. It is also called negative feedback system
since the output is feedback to the inverting input terminals. The differential voltage Vd at the
inverting input terminal of the op-amp is zero ideally and the output voltage is given as,

Vo = ACL Vi

Here the output voltage is in phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the non - inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.
PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:

Gain of an inverting amplifier Av=V o/Vin = 1+Rf/ Ri,

Let the required gain be 11,
Therefore Av= 1+Rf/ Ri= 11

Rf/ Ri = 10
Take Ri= 1KΩ, Then Rf = 10KΩ

Vin = 1Vpp

Vo = ?
Gain Av = Vo/Vin =?
Observed phase difference between the input and the output on the CRO =?

CALCULATION:
OBSERVATIONS:

S.No Input Output

Amplitude
1. ( No. of div x Volts per div )

Time period
2. ( No. of div x Time per div )

MODEL GRAPH:

Non-Inverting amp
Vin
(V)
t(sec)

Vo
(V)

t(sec)

RESULT:

The design and testing of the Non-inverting amplifier is done and the input and output waveforms
were drawn.

VIVA QUESTIONS:
1. What is an op-amp?
2. What is an non- inverting amplifier?
3. What is the difference between inverting and non- inverting amplifier?
4. Define CMRR.
5. Write the equation for gain of an non- inverting amplifier.
 2. OPAMPAPPLICATIONS - A D D E R , SUBTRACTOR CIRCUITS

AIM: To study the applications of IC 741 as adder, Subtractor.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required

CIRCUIT DIAGRAM:

ADDER:
SUBTRACTOR:

THEORY:

ADDER:

Op-Amp may be used to design a circuit whose output is the sum of several input
signalssuchascircuitiscalledasummingamplifierorsummer.Wecanobtaineither inverting or non-
inverting summer.

Thecircuitdiagramsshowsatwoinputinvertingsummingamplifier.Ithastwo input voltages V1

and V2, two input resistors R1, R2and a feedback resistor Rf.

Assuming that op- amp is in ideal conditions and input bias current is assumed to be zero, there
is no voltage drop across the resistor Rcomp and hence the non-inverting input terminal is at ground
potential.
By taking nodal equations.

V1/R1+V2/R2+V0/Rf=0
V0=-[(Rf/R1) V1+(Rf/R2) V2]
And here
R1=R2=Rf=1KΩ
V0=- (V1+V2)
Thus output is inverted and is sum of input.
SUBTRACTOR:

A basic differential amplifier can be used as a Subtractor. It has two input signals V1and V2and two
input resistances R1andR2 and a feedback resistor Rf.The input signals scaled to the desired values
by selecting appropriate values for the external resistors.

From the figure, the output voltage of the differential amplifier with a gain of‘1’ is

V0=-R/Rf(V2-V1)
V0=V1-V2.
Also R1=R2=Rf=1KΩ.

Thus, the output voltage V0 is equal to the voltage V1applied to the non-inverting terminal minus
voltage V2 applied to inverting terminal.
Hence the circuit is sub tractor.

OBSERVATIONS:

ADDER:

V1(volts) V2(volts) Theoretical Practical

V0=-(V1+V2) V0 =-(V1+V2)

SUBTRACTOR:

V1(volts) V2(volts) Theoretical Practical

V0=(V1-V2) V0 =(V1-V2)
MODEL GRAPH:

PROCEDURE:

ADDER:

1. Connections are made as per the circuit diagram.

2. Apply input voltage1) V1=5v,V2=2v
2) V1=5v,V2=5v
3) V1=5v,V2=7v.
3. Using Millimeter measure the dc output voltage at the output terminal.
4. For different values of V1and V2measure the output voltage.

SUBTRACTOR:

1. Connections are made as per the circuit diagram.

2. Apply input voltage1) V1=5v,V2=2v
2) V1=5v,V2=5v
3) V1=5v, V2=7v.
3. Using multi meter measure the dc output voltage at the output terminal.
4. For different values of V1and V2measure the output voltage.

PRECAUTIONS:

1. Make null adjustment before applying the input signal.

2. Maintain proper Vcc levels.

RESULT:
 3. OPAMPAPPLICATIONS- COMPARATOR CIRCUITS

AIM: To study the applications of IC 741 as Comparator.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors (1KΩ)—4
7. Connecting wires and probes As required

CIRCUIT DIAGRAM: COMPARATOR

THEORY:

COMPARATOR:

A comparator is a circuit which compares a signal voltage applied at one input of an op -

ampwithaknownreferencevoltageattheotherinput.Itisbasicallyanopen loop op-amp with
output ±Vsat as in the ideal transfer characteristics.

It is clear that the change in the output state takes place with an increment in input Vi of only
2mv.Thisistheuncertaintyregionwhereoutputcannotbedirectly defined There are basically 2 types
of comparators.

1. Non inverting comparator and.

2. Inverting comparator.

The applications of comparator are zero crossing detector, window detector, time marker
generator and phase meter.
PROCEDURE:
1. Refer the pin diadram of Op Amp IC741&assemble the basic comparator in non-inverting
configuration circuit as per the circuit diagram on the breadboard.
2. Set the DC power supply to provide +Vcc & -VEE = +12V at the respective pins of the Op
Amp IC.
3. Set the function generator to provide 16Vp-p sine wave at 1Khz freq.& apply the AC input
at pin no 2(Inv) of the Op-Amp IC741.
4. Set the DC power supply to provide the 2Vreference voltage by making necessary
adjustment & apply this reference voltage signal at pin no 3 of the OP Amp IC741.
5. Observe the input sinusoidal at channel 1& the corresponding output square wave at
channel 2 of CRO & note down the amplitude.
6. Overlap the input & output waves and note down the voltage position on sine wave,where
the output changes its statethis voltage denote the reference voltage.

COMPARATOR:

Voltage input Vref Observed square wave

amplitude
PRECAUTIONS:

1. Make null adjustment before applying the input signal.

2. Maintain proper Vcc levels.

RESULT:
 4. INTEGRATOR AND DIFFERENTIATOR.

4(a) INTEGRATOR:

AIM:

To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Capacitors As required
8. Connecting wires and probes As required

THEORY:

A circuit in which the output voltage waveform is the integral of the input voltage waveform is
the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the
feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given
as,
Vo = - (1/Rf C1 ) ∫ Vi dt

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input
signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa <
fb . The input signal will be integrated properly if the Time period T of the signal is larger than or
equal to Rf Cf . That is, T ≥ Rf Cf

The integrator is most commonly used in analog computers and ADC and signal-wave shaping
circuits.

PIN DIAGRAM:
CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:
Given f =1 KHz
So T = 1/f = 1ms
Design equation is T = 2πRiC

Let C = 0.01µF
Then Ri = 15KΩ
Take Rf = 10Ri = 150KΩ

[ To obtain the output of an Integrator circuit with component values R1 Cf = 0.1ms , Rf = 10 R1

and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.]

We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)

Therefore fb =
Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2π Rf Cf)
We get , R 1 = and hence R f =

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.
OBSERVATIONS:

S.No amplitude Time period

Sine wave input

1.
Cosine wave output
Square wave input
2.
Spike wave output

MODEL GRAPH:

Model graph
Vin

Vo

CALCULATION:

RESULT:

The design of the Integrator circuit was done and the input and output waveforms were obtained.
 4(b) DIFFERENTIATOR

AIM: To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required

THEORY:

The differentiator circuit performs the mathematical operation of differentiation; that is, the
output waveform is the derivative of the input waveform. The differentiator may be constructed
from a basic inverting amplifier if an input resistor R 1 is replaced by a capacitor C 1 . The
expression for the output voltage is given as,

Vo = - Rf C1 ( dVi /dt )

0
Here the negative sign indicates that the output voltage is 180 out of phase with the input
signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-
amp to compensate for the input bias current. A workable differentiator can be designed by
implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1 < 1 µF, calculate the value of R f.
2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1 C1 = Rf Cf.
 The differentiator is most commonly used in wave shaping circuits to detect high frequency
components in an input signal and also as a rate–of–change detector in FM modulators.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN :

Given f = 1 KHz
So T = 1/f = 1ms
Design equation is T = 2πRfC

Let C = 0.01µF

Then R f = 15KΩ

Let Ri = Rf/10 = 1.5KΩ

[To design a differentiator circuit to differentiate an input signal that varies in frequency from 10
Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to the differentiator, draw its
output waveform.]
Given fa = 1 KHz
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1 )
Let us assume C1 = 0.1 µF; then
Rf =
Since fb = 20 fa , fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 =
Also since R1C1 = Rf Cf ; Cf =
Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin ωt
We know ω = 2πf
Hence
Vo = - Rf C1 ( dVi /dt )
= - 0.94 cos ωt

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.

OBSERVATIONS:

S.No amplitude Time period

1. Sine wave input

Cosine wave output

2. Square wave input

Spike wave output

MODEL GRAPH:
Model graph
Vin
Model graph
IV
Vin
IV
t

t
-IV

-IV

2V

Vo

t
t

-2V

CALCULATION:

RESULT:
The design of the Differentiator circuit was done and the input and output waveforms were
obtained.

VIVA QUESTIONS.
1. Define an integrator.
2. State the applications of an integrator.
3. What is a differentiator?
4. What are the steps to design a differentiator?
5. What are the steps to design an integrator?
 5. ACTIVE LPF & HPF

5a. FIRST ORDER BUTTERWORTH LOW PASS FILTER

Aim: To design and obtain the frequency response of first order Low Pass Filter (LPF)

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1 IC 741/IC TL082 - 1
2 Function Generator (0 – 3MHz), 20V p-p 1
3 CRO 30 MHz 1
4 Dual RPS (0-30)V 1
5 Resistors 1KΩ,2.2 KΩ,3.2 KΩ 1
6 Capacitors 0.1μF 1
7 Connecting Wires - As Required
8 Bread Board - 1

CIRCUIT DIAGRAM:
DESIGN:
A low pass filter can be designed by implementing the following steps
1. Choose a value of high cut off frequency fH.
2. Select a value of C less than or equal to 1µF.
1
3. Calculate the value of R using 𝑅 =
2𝜋𝑓𝐻𝐶
4. Finally select the values of R1 and Rf dependent on the desired pass band gain Af
using
𝑅𝑓
𝐴𝑓 = (1 + )
𝑅1
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Apply sinusoidal wave of constant amplitude at the input such that op-amp does not go into
saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in
Table.

Table:
Vin=2VPP

Frequency in Output voltage in Gain in

S.No Gain
Hz Volts dB
1.
2.
3.
4.
5.
Theoretical calculations:
Given
Voltage Gain Af =
Highest cut off frequency = fH =

1 =
Assume C = 0.1µF Calculate 𝑅=
2𝜋𝑓𝐻𝐶

Assume R1 = 1KΩ calculate Rf from the gain expression

𝑅𝑓
𝐴𝑓 = (1 + )
𝑅1

Rf =

MODEL WAVEFORM:

RESULT:
 5b. FIRST ORDER BUTTERWORTH HIGH PASS FILTER

Aim: To design and obtain the frequency response of first order High Pass Filter (LPF)

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1 IC 741/IC TL082 - 1
2 Function Generator (0 – 3MHz), 20V p-p 1
3 CRO 30 MHz 1
4 Dual RPS (0-30)V 1
5 Resistors 1KΩ,2.2 KΩ,3.2 KΩ 1
6 Capacitors 0.1μF 1
7 Connecting Wires - As Required
8 Bread Board - 1

CIRCUIT DIAGRAM
DESIGN:
A low pass filter can be designed by implementing the following steps
1. Choose a value of high cut off frequency fH.
2. Select a value of C less than or equal to 1µF.
1
3. Calculate the value of R using 𝑅 =
2𝜋𝑓𝐿𝐶
4. Finally select the values of R1 and Rf dependent on the desired pass band gain Af using
𝑅𝑓
𝐴𝑓 = (1 + )
𝑅1
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Apply sinusoidal wave of constant amplitude at the input such that op-amp does not go
into saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in
Table.

Table:
Vin=2VPP

Frequency in Output voltage in Gain in

S.No Gain
Hz Volts dB
6.
7.
8.
9.
10.
11.
Theoretical calculations:
Given
Voltage Gain Af =
Highest cut off frequency = fH =

1 =
Assume C = 0.1µF Calculate 𝑅=
2𝜋𝑓𝐻𝐶

Assume R1 = 1KΩ calculate Rf from the gain expression

𝑅𝑓
𝐴𝑓 = (1 + )
𝑅1

Rf =

RESULT:
 6. IC741 To Generate Square/Triangular Wave

6(a). Square Wave Generator

Aim: To Design an Astable Multivibrator to generate square waveform for the given specifications
using op-amp.
APPARATUS REQUIRED:

S. No. Equipment/Component name Specifications/Value Quantity

1 IC 741/IC TL 082 1

2 Resistors 10kΩ 3
3 Capacitor 0.01µF 1
4 Regulated Power supply (0 – 30)V 1
5 Cathode Ray Oscilloscope 20MHz 1
6 Connecting wires -
7 Bread board trainer 1

Circuit Diagram
Triangular Wave Generator

0
Calculations:
Square Wave signal
1+β
Total time period: 𝑇 = 2𝑇1 = 2𝑅𝐶 𝑙𝑛 ( )
1−𝛽
The output swings from +V sat to –Vsat. So V O(PP)=2V sat

Triangular Wave signal

Procedure:
Square wave generator:
1. Connect the circuit as shown in figure:
2. Apply the power supplies as VCC = +10V and VEE = -10V.
3. Observe the output at terminal Vo .
4. Measure the frequency of the oscillations.
5. Compare the Theoretical and Practical frequency values.
6. Plot the output waveform.

Triangular wave generator:

1. Connect the circuit as shown in figure:
2. Apply the power supplies VCC = +10V and VEE = -10V.
3. Observe the square waveform at the output terminal VO2.
4. Measure the frequency of the oscillations.
5. Compare the Theoretical and Practical frequency values.
6. Plot the output waveform.
Table:

Practical
Theoretical
S. Square wave Triangular wave
No. Time Time output Time output
Frequency Frequency Frequency
period period voltage period voltage
F (KHz) F (KHz) F (KHz)
T (ms) T (ms) V0 (V) T (ms) V0 (V)

MODEL WAVEFORM:
Result:

VIVA QUESTIONS:

1. List the advantages of active filters over passive filter.

2. Derive fH of second order LPF.

3. Draw the frequency response for ideal and practical of all types of filters.

4. Design a first order low pass filter for 2 KHz frequency.

 7. Mono-stable Multivibrator using IC555

Aim: To design a Monostable Multivibrator using 555 timer to get pulse output.

Apparatus:

S.No. Equipment/Component name Specifications/Value Quantity

1 555 Timer - 1
2 Regulated Power supply (0 – 30)V 1
3 Function Generator (0 – 3MHz), 20V p-p
4 Cathode Ray Oscilloscope 30 MHz 1
5 Resistors 6.8KΩ, 1
6 Capacitors 1μF,0.01μF 1
7 Connecting wires - Required

Circuit Diagram:
MONOSTABLE MULTIVIBRATOR

DESIGN:
Step 1: Choose C=1μF.
Step 2: Since in Monostable Multivibrator, tp=1.1RC. Therefore R= tp / 1.1C
Step 3: Using above equation, design the value of R.
 PROCEDURE:
1. Connect the 555 timer in Monostable mode as shown in fig.
2. Connect the C.R.O at the output terminals & observe the output.
3. Apply external trigger at the trigger input terminal (PIN 2) and observe the output of Monostable
Multivibrator.
4. Record the trigger input, voltage across the capacitor & output waveforms and measure the
output pulse width.
5. Verify results with the sample output waveforms as shown in fig
6. Calculate the time period of pulse (tp =1.1RC) theoretically & compare it with practical values.

Table:

Theoretical Values Practical Values

f f
S.No tc td T tc td T
(in D (in D
(m.sec) (m.sec) (m.sec) (m.sec) (m.sec) (m.sec)
Hz) Hz)

MODEL WAVEFORM:

Result:
 8. Astable Multivibrator using IC555

Aim: To design an Astable Multivibrator using IC 555 timer to generate a square wave of 6.9 KHz
with 52.38 % Duty Cycle.

Apparatus Required:

S.No. Equipment/Component name Specifications/Value Quantity

1 555 Timer - 1
2 Regulated Power supply (0 – 30)V 1
3 Function Generator (0 – 3MHz), 20V p-p
4 Cathode Ray Oscilloscope 30 MHz 1
5 Resistors 1KΩ,10 KΩ 1
6 Capacitors 0.1μF,0.01μF 1
7 Connecting wires - Required

Circuit Diagram:
 PIN DIAGRAM:

DESIGN:

T = 0.69 (RA + 2RB) C or f = 1.44 / {( R A+2RB) C}, Here T = T1 + T2

T1 = 0.69(RA+RB)C (charging)

T2 = 0.69(RB)C (discharging)
Let T1 = 1ms ; T2 = 0.5ms ; C = 0.1 Μf,
0.69 RB C = 0.5ms R B = 7.2 KΩ = 6.8KΩ
(std), 0.69 (R A+RB) C = 1ms
RA + RB = 14.49 KΩ, RA = 14.49- RB, RA = 7.2 KΩ = 6.8KΩ

PROCEDURE:
1. Connect the IC 555 timer in Astable mode as shown in fig.
2. Connect the C.R.O at the output terminal (pin 3) and observe the output.
3. Record the waveforms at pin3, across the capacitor & compare them with the sample output
waveforms as shown in fig.
4. Measure the charging time (tc), discharging time (td) and total time period/ Frequency from the
output waveform.
5. Calculate tc, td, time period (T), frequency (f) of the square wave output and percentage duty
cycle theoretically.
6. Compare the theoretical values charging time (tc), discharging time (td) ,total time period/
Frequency & % Duty cycle with the practical values.
Table:

Theoretical Values Practical Values

S.No f
tc td T tc td T f
(in D D
(m.sec) (m.sec) (m.sec) (m.sec) (m.sec) (m.sec) (in Hz)
Hz)

Model Waveform:

Result:

QUESTIONS:

1. What is the other name for Astable multivibrator (AMV)?

2. What is the formula for the time period of the waveform of AMV?
3. What is the formula for the % of Duty cycle?
4. Write any three applications of a Astable multivibrator circuit?
5. Can a Astable multivibrator circuit be used to produce Sinusoidal waveforms. Why?
 9. SCHMITT TRIGGER

Aim: To construct and study the Schmitt Trigger using IC741 Operational Amplifier.

Apparatus Required:

S.No Name of the Apparatus Range Quantity

1 IC 741/IC TL082 - 1
2 Function Generator (0 – 3MHz), 20V p-p 1
3 CRO 30 MHz 1
4 Dual RPS (0-30)V 1
5 Resistors 1KΩ 2
6 Connecting Wires - As Required
7 Bread Board - 1

Circuit Diagram:

Procedure:

1. Connect the circuit as shown Fig.

2. Set Function Generator output for sine wave signal of Amplitude at 1V(p-p) & frequency 1KHz.
3. Set R1 and R2 values at fixed positions and note down the values in tabular column.
4. Calculate theoretical values of V UT and V LT and note down the values in tabular column.
(+Vsat = 10V,- Vsat = -10V).
5. Apply Function Generator output at input terminals Vi, connect C.R.O- CH2 at output terminals
Vo, C.R.O-CH1 at input terminals Vi.
 6. Observe square wave output on C.R.O for the given input sine wave & compare them with the
sample waveform as shown in fig.
7. Note down the practical V UT, VLT and VH values in tabular column.
8. Compare the theoretical and practical values of VUT, VLT and VH.

Table:

Theoretical Values Practical Values

S. No
R1 R2 VUT VLT VH VUT VLT VH

Calculations:

VUT =

VLT =

Model Waveform
 RESULT:

VIVA QUESTIONS:

1. How can a comparator be converted to Schmitt trigger

2. What do you mean by the Phenomenon hysteresis or backlash?
3. Why do we call Schmitt trigger as square wave generator.
4. What are the applications of Schmitt trigger?
5. Design a Schmitt trigger with an UTP =3V and LTP=5V and an input voltage of 10v.
 10 (a). Voltage Regulator using IC 723

Aim :Study the operation of Voltage regulator using IC 723.

Apparatus:

 Bread board
 IC LM723 - 1No.
 Resistors(1KΩ, 2.7KΩ, 4.7KΩ, 6.8KΩ) - 1No. each
 RPS
 DRB / Potentiometer 10K - 1No.
 Capacitors 100pF - 1No.
 Connecting wires
 Ammeter 0-20 mA - 1No.
 Voltmeter 0-20V - 1No.

Circuit Diagrams:

a). To get output voltage > 7V

Circuit Diagram:

b. To get output voltage < 7V

Procedure:

I. LINE REGULATION

1. Connections are made as per the circuit diagram.

2. RPS is connected as Vi.
3. A fixed load of 1K is kept at the output.
4. Input Vi is varied from 15V to 25V in steps of 2V and Output voltage is measured.
5. Graph is drawn between the input voltage and output voltage.

II. LOAD REGULATION

1. Connections are made as per the circuit diagram.

2. RPS is connected as Vi.
3. Output voltage is measured by varying the load (Potentiometer), in steps of 1mA
4. Graph is drawn between the output voltage and output current (load).
Observations:

Line regulation = (ΔVout / ΔVin) / 100%

Vnl =

Line Voltage (V) Output Voltage (V)

Load regulation

Regulated Output (V) Load Current(mA) Load Resistance(KΩ) Load Regulation

% Regulation = [(Vnl - Vfl) / Vfl] * 100

Model Graph:

Result:
10 (b). Voltage Regulator using Three Terminal Voltage Regulators - 7805, 7809, 7912

Aim: Study the operation of Three terminal fixed Voltage regulators using ICs 78xx / 79xx
(Positive and Negative Voltage Regulators)

Apparatus:

1. Bread board
2. ICs 7805, 7809, 7912 ICs - 1No. each
3. RPS
4. DRB / potentiometer 10KΩ - 1No.
5. Capacitors 1000µF, 22 µF - 1No. each
6. Voltmeter - 0-20V
7. Connecting wires

Circuit Diagram:

Figure.1 Fixed Positive Voltage regulator

Figure.2 Fixed Negative Voltage Regulato

Procedure:

For fixed positive voltage regulator (7805 and 7809):

1. Connect the circuit diagram as shown in figure.1.

2. Apply the unregulated voltage to the IC 7805 and note down the regulator output voltage.
Vary input voltage from 7V to 20V and record the output voltages.
3. Calculate the line regulation of the regulator using the formula.
4. Line Regulation = ΔVO /ΔVi.
5. Now, fix the input voltage as 15V and vary the load resistance RL, from 1K to 10 K ohms.
Note down the regulator output voltage.
6. Calculate the Load regulation of the regulator using the formula.
7. Load Regulation =ΔV O / ΔIL.
8. Repeat the above procedure for 7809.

For fixed negative voltage regulator (7912):

1. Connect the circuit diagram as shown in figure.2.

2. Apply the unregulated voltage to the IC 7912 and note down the regulator output voltage.
3. Vary input voltage from 7V to 20V and record the output voltages.
4. Calculate the line regulation of the regulator using the formula.
5. Line Regulation = ΔV O / ΔVi.
6. Now, fix the input voltage as 15V and vary the load resistance RL, from 1K to 10 K ohms.
Note down the regulator output voltage.
7. Calculate the Load regulation of the regulator using the formula.
8. Load Regulation =ΔV O / ΔIL.

Observations:

1). For +Ve Voltage Regulator 7805

Line Regulation: (RL is constant)

S.No. Unregulated DC Input, Vi in Volts Regulated DC Output, VO in Volts

Load Regulation: (Vi is constant)

Load Resistance, RL in Ohms Regulated DC output, VO in Volts

2). For +Ve Voltage Regulator 7809

Line Regulation: (RL is constant)

No. Unregulated DC Input, Vi in Volts Regulated DC Output, VO in Volts

Load Regulation: (Vi is constant)

S.No. Load Resistance, RL in Ohms Regulated DC output, VO in Volts

3). For -Ve Voltage Regulator 7912

Line Regulation: (RL is constant)

S.No. Unregulated DC Input, Vi in Volts Regulated DC Output, VO in Volts

Load Regulation: (Vi is constant)

S.No. Load Resistance, RL in Ohms Regulated DC output, VO in Volts

Model Graphs(for +Ve Voltage Regulators):

Fig 3. Line Regulation

Fig 4. Load Regulation

Model Graphs (for -Ve Voltage Regulator):

Figure 5. Line Regulation for 79XX

Figure 6. Load Regulation for 79XX

Result:
 11. R-2R DIGITAL TO ANALOG CONVERTER

Aim : To design 4 bit R-2R ladder DAC using Op-Amp for an output voltage of 5 V when the
input is 10 (Binary 1010).

Apparatus :

Sl.
Particulars Specification Quantity
No.
1. IC µA741 02
2. Resistors As per design -
3. Multimeter - 01
4. Base board + connecting wires - 01 Set

Circuit Diagram
 Procedure :
1. Connections are made as shown in the circuit diagram.
2. Digital input data is given at D3, D2, D1, D0 and corresponding analog output voltage V0 is
measured.
3. Tabulate the readings & plot the graph between Vo on y-axis Vin on X-axis.
Note :
1. D0.D1.D2 & D3 are binary input.
2. Vo is the analog output.
3. Binary inputs Do.D1.D2 & D3 can take either the value ‘0’ or ‘1’.
4. Binary input Di (i = 0 to 3) can be made ‘0’ by connecting the i/p to ground. It can be made
‘1’ by connecting to –5 V.

Logic 0 0V

Logic 1 +5V

Binary Inputs Analog O/P Analog O/P

Decim Vo(volts) Vo(volts)
D3 D2 D1 D0
al
Value Theoretical Practical values
values
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

Result :
 12. Parallel Comparator Type, Counter Type, and Successive Approximation ADC
Aim :
Design of Parallel Comparator Type, Counter Type, and Successive Approximation ADC and Evaluation of Their
Efficiency

Apparatus Required:
1. Op-amps (for comparators)
2. DAC module
3. Digital counter (for Counter type ADC)
4. SAR logic circuit (for SAR ADC)
5. Analog input source
6. Microcontroller / FPGA (optional for implementation)
7. Power supply
8. Breadboard and connecting wires
9. Oscilloscope (for output observation)

Theory:
1. Parallel Comparator (Flash) ADC
 Uses 2n−12^n - 12n−1 comparators for n-bit resolution.
 Fastest type of ADC.
 Analog input is simultaneously compared with all reference voltages.
 Output is encoded using a priority encoder.
Efficiency:
 Speed: Very high (single clock cycle)
 Hardware complexity: High
 Number of comparators = 2n−12^n - 12n−1

2. Counter Type ADC

 Uses an up-counter and DAC.
 Counter starts at 0 and increments until DAC output ≥ analog input.
 Simple but slow due to counting from 0 for every sample.
Efficiency:
 Speed: Low (depends on resolution)
 Time per conversion T=2n×TclockT = 2^n \times T_{clock}T=2n×Tclock

3. Successive Approximation ADC

 Uses SAR logic and DAC.
 Starts with MSB and narrows down using binary search.
 Balanced in terms of speed and complexity.
Efficiency:
 Speed: Medium (n clock cycles for n-bit resolution)
 Time per conversion T=n×TclockT = n \times T_{clock}T=n×Tclock
Circuit Diagrams:

Procedure:
For all ADCs:
1. Connect the analog input signal (e.g., potentiometer or sine wave).
2. Build the circuit based on the selected ADC type.
3. Observe and record the digital output.
4. Compare analog input with DAC output (for SAR and Counter types).
5. Measure conversion time using oscilloscope or logic analyzer.

Observations and Calculations:

ADC Type Resolution (n bits) Number of Comparators Conversion Time (T) Efficiency (%)
Flash ADC
Counter ADC
SAR ADC

Note: Efficiency = 1Average number of cycles for conversion×100%\frac {1} {\text {Average number of cycles
for conversion}} \times 100\%Average number of cycles for conversion1×100%

Result:

Viva Questions:
1. Why does Flash ADC require 2n−12^n - 12n−1 comparators?
2. What is the role of DAC in SAR and Counter ADC?
3. How can SAR ADC achieve binary search?
4. Compare power consumption of the three ADCs.
5. Why is the Counter ADC slower than the SAR ADC?
 13. 8X1 MULTIPLEXER-74X151

AIM: To construct multiplexer and de-multiplexer circuits using IC-74X151.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 74151 1
1
74155 1
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards

4 Fixed Power Supply (0-5v) 1

74LS151 MULTIPLEXER

PIN DIAGRAM FUNCTIONAL DIAGRAM

 THEORY:

The multiplexers contains full on-chip decoding unit to select desired data source.
The 74151 selects one-of-eight data sources. It has a enable input which must be at a LOW
logic level to enable these devices. These perform parallel-to-serial conversion. The 74150
selects one-of sixteen data sources.
The 74155 sends the data source to one of four data destinations. It has a enable
input which must be at a LOW logic level to enable these devices.
The binary decoder with enable input connected to data line known as De multiplexer.

PROCEDURE:

1. Connections are made as per the logic diagram.

2. Apply +5V for Vcc & 0V for GND
3. Outputs will be verified for different combinations of inputs.

FUNCTION TABLE:
INPUTS OUTPUTS
S.NO
E C B A D0 D1 D2 D3 D4 D5 D6 D7 Y Y
1 H X X X X X X X X X X X H L
2 L L L L L X X X X X X X
D'0 D0
3 L L L L H X X X X X X X
4 L L L H X L X X X X X X
D'1 D1
5 L L L H X H X X X X X X
6 L L H L X X L X X X X X
D'2 D2
7 L L H L X X H X X X X X
8 L L H H X X X L X X X X
D'3 D3
9 L L H H X X X H X X X X
10 L H L L X X X X L X X X
D'4 D4
11 L H L L X X X X H X X X
12 L H L H X X X X X L X X
D'5 D5
13 L H L H X X X X X H X X
14 L H H L X X X X X X L X
D'6 D6
15 L H H L X X X X X X H X
16 L H H H X X X X X X X L
D'7 D7
17 L H H H X X X X X X X H
 Logic Diagram

RESULT:-
 14. DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM:To design and implement 4-bit adder and Subtractor using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:

2 BIT BINARY ADDER

 LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are connected
in chain through the full adder. The input carry to the adder is C 0 and it ripples through
the full adder to the output carry C 4 .
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry C 0
must be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit
is adder circuit. When M=1, it becomes Subtractor.
4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot
be greater than 19, the 1 in the sum being an input carry.

The output of two decimal digits must be represented in BCD and should appear in the
form listed in the columns.ABCD adder that adds 2 BCD digits and produce a sum digit in
BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder
to produce the binary sum.

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:-
 15. DECADE COUNTER (74LS90)

AIM:To verify the working of a decade counter using digital IC.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 IC 74LS90 Decade Counter IC 1

2 Connecting Wires - As Required
3 Bread Board Trainer - 1

PIN DIAGRAM FUNCTIONAL DIAGRAM

PROCEDURE:

1. D0,,D1,………D7 are the inputs of the MUX,A,B,C,EN are select inputs and Q is the
output.
2. With EN is High Y=0 if EN is Low then for an input data word, checked the outputs Y and
Y’ for various combinations of selected inputs.
3. Compare with the tabulated results.
FUNCTIONAL TABLE:

R01 R02 Sg1 Sg2 Q3 Q2 Q1 Q0

H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

TRUTH TABLE:

OUTPUT
COUNT
Q3 Q2 Q1 Q0
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H

RESULT:
 16. UNIVERSAL SHIFT REGISTER (74LS194)

AIM : To study the shift right logic, shift left logic, parallel load applications withUniversal shift using
IC 74194.

APPARATUS:

S.No Name of the Apparatus Range Quantity

1 IC 74LS194 Universal Shift Register IC 1

2 Connecting Wires - As Required
3 Bread Board Trainer - 1

PIN DIAGRAM:

PIN DESCRIPTION:

PIN SYMBOL DESCRIPTION

1 MR Asynchronous matter
2 DSR Serial data input (shift right)
3 D0 Parallel data input
4 D1 Parallel data input
5 D2 Parallel data input
6 D3 Parallel data input
7 DSL Serial data input (shift left)
8 GND Ground
 9 S0 Mode control input
10 S1 Mode control input
11 CP Clock input (low, high, edge triggered)
12 Q3 Parallel output
13 Q2 Parallel output
14 Q1 Parallel output
15 Q0 Parallel output
16 VCC Supply Voltage

PROCEDURE:
1. Reset all outputs by making MR=0.
2. SHIFT LEFT REGISTERS: Made MR=1 and s1s0=10. Applied DSL=1 and observed
Q0,Q1,Q2,Q3 for 4 clock pulses. Then made DSL=0 and observed Q0,Q1,Q2,Q3 for 4 clock
pulses.
3. SHIFT RIGHT REGISTERS: Made MR=1 and s1s0=01. Applied DSR=1 and observed
Q0,Q1,Q2,Q3 for 4 clock pulses. Then made DSR=0 and observed Q0,Q1,Q2,Q3 for 4 clock
pulses
4. PARALLEL LOAD: Made MR=1 and s1s0=11 to transfer the data parallel to output at the
clock positive transition change the input data and observed the change at the output
5. HOLD: Made MR=1 and s1s0=00 then the shifting operation is ceased and output would show
previous one.

INPUTS OUTPUTS
OPERATION MODE CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3
RESET X 0 X X X X X 0 0 0 0
before clock → Q0 Q1 Q2 Q3
1 1 0 X 1 X Q1 Q2 Q3 1
↑
SHIFT LEFT 1 1 0 X 0 X Q1 Q2 Q3 0
before clock → Q0 Q1 Q2 Q3
1 0 1 1 X X 1 Q0 Q1 Q2
↑
SHIFT RIGHT 1 0 1 0 X X 0 Q0 Q1 Q2
PARALLEL LOAD ↑ 1 1 1 X X Dn D0 D1 D2 D3
HOLD X 1 0 0 X X X Q0 Q1 Q2 Q3

RESULT:
 17. 3 TO 8 DECODER-74LS138
AIM: To verify operation of the 3 to 8 decoder using IC 74138.

APPARATUS:

S.NO APPARATUS IC NUMBER QUANTITY

1 IC 74LS138 1

2 Digital IC Trainer Kit 1

3 Patch cards REQUIRED

4 Fixed Power Supply (0-5v) 1

THEORY:

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to a
maximum of 2 n unique output lines .The IC 74138 accepts three binary inputs and when enable
provides 8 individual active low outputs. The device has 3 enab le inputs .Two active low and one
active high.

PROCEDURE:-
1. Make the connections as per the circuit diagram.

2. Change the values of G1, G2A, G2B, A, B, and C, using switches.

3. Observe status of Y0, to Y7 on LED’s.

4. Verify the truth table.

PIN DIAGRAM:
LOGIC DIAGRAM:

RESULT:-

VIVA QUESTIONS:

1. What do you understand by decoder?

2. What is de-multiplexer?

3. What do you understand by encoder?

4. What is the main difference between decoder and demultiplexer?

5. Why Binary is different from Gray code?

 18. Up/Down counter using 74Ls163

Aim: To Design an UP/Down counter using 74LS163

Apparatus Required:

S.NO APPARATUS IC NUMBER QUANTITY

1 IC 74LS138 1

2 Digital IC Trainer Kit 1

3 Patch cards REQUIRED

4 Fixed Power Supply (0-5v) 1

Pin Diagram

Pin Pin
Description
Number Number Description
1 Active Low Clear Input 9 Active low Load Input
2 Clock Signal Input 10 Active High ENT Input
3 A(LSB) 11 Qd(MSB)
4 B 12 Qc
Preset Inputs to Load Data Flip-Flop Outputs
5 C 13 Qb
6 D(MSB) 14 Qa(LSB)
7 Active High Input ENP 15 RCO(Ripple Carry Output logic 0 to 1)
8 Ground 16 Vcc
Mod 7 Counter Using IC 74163

Truth Table:
Clear Load ENT ENP Action on the rising clock edge
0 X X X All 4 flip-flop outputs cleared
Load preset inputs data(A, B, C, & D) to
1 0 X X Qn
1 1 1 1 Increment Count
1 1 0 X No change (Hold)
1 1 X 0 No change (Hold)

Procedure
1. Make the connections as per the circuit diagram.

2. Verify the truth table.

Result