ICT: Manufacturing of Integrated Circuits

A short (and simplified) summary

12 March 2025
Luca Benini
Frank K. Gürkaynak
Where are we in the lecture
▪ Our lecture is about how to design ICs,
▪ We have covered some basics
▪ Business side of IC Design and how open source EDA fits in (Lecture 1)
▪ Front-end design and a System Verilog Refresher (Lecture 2)
▪ Synthesis and CMOS gates (Lecture 3)
▪ A brief intro to our example design (Croc) which we use for exercises and projects
▪ Simple refresher on (RISC-V) cores
▪ Components of Croc and how they are connected
▪ Now it is time to jump into meat of VLSI2
▪ How are ICs manufactured (simplified)
▪ Will help us understand some of the constraints of IC Design better

VLSI 2: From Netlist to Complete System on Chip 2

Where are we
Week Short Content
1 INTRO Why this course, design flow, case for an open-source EDA flow
2 RTL Refresher on System Verilog
3 Netlist Logic synthesis, basics of digital circuit timing, Croc our example SoC we will use in class
4 ICT Short summary of IC manufacturing
5 LEF Standard cells, routing layers
6 DEF Floorplanning, I/O rings, ESD structures, packaging
7 LIB Timing, Clock trees, Process corners
8 SDF Parasitics, extraction, issues in timing, crosstalk
9 GDS Placement, routing, chip finishing, DRC and LVS
10 VCD Power analysis and IR Drop
11 Project Discussion on your final project, Q&A session
12 WGL IC Testing, ATPG, JTAG, BIST
13 PPA Properly reporting performance, power, area in IC Design
14 Final Final thoughts, reserve

VLSI 2: From Netlist to Complete System on Chip 3

Goals for this lecture
▪ Understand the materials that we use for building ICs
▪ Conductors, insulators, semiconductors
▪ What is MOS technology, why is it great
▪ What is so special about the transistor
▪ Basic steps of manufacturing
▪ (Photo)lithography, implantation, material deposition, etching, cleaning, polishing
▪ The challenges involved in finding matching materials with good properties
▪ Step by step instructions for manufacturing
▪ Using a rather conventional process
▪ To get an idea about what is involved
▪ Will help us understand what limitations are

VLSI 2: From Netlist to Complete System on Chip 4

Watch this video – Matt explains the process at IHP

https://www.youtube.com/watch?v=aBDJQ9NYTEU

VLSI 2: From Netlist to Complete System on Chip 5

To conduct or not to conduct
Conductors Insulators
▪ We need electrical current ▪ Need to separate conductors
▪ Power ▪ We need multiple signals, power
▪ Signals ▪ Ideally perfect separation
▪ Ideally no losses ▪ No current flow between conductors
▪ Defined by conductivity (ρ) ▪ Other issues
▪ Material should not have resistance ▪ Dielectric constant/permitivity (ε)
▪ Some materials are better ▪ We want this high for capacitors
▪ Other issues ▪ Low if we are avoiding parasitic capacitance
▪ Need to be compatible to process
▪ Need to be compatible to process

VLSI 2: From Netlist to Complete System on Chip 6

What is the deal with Semiconductors ?

VLSI 2: From Netlist to Complete System on Chip 7

We can replace atoms in this perfect structure

VLSI 2: From Netlist to Complete System on Chip 8

 … and give some electrical character

Basically, it is not the semiconductor,

but the doping that makes it interesting

VLSI 2: From Netlist to Complete System on Chip 9

What is so great about semiconductors
▪ You can “engineer” its properties
▪ Make it P type by injecting type-III elements (B, Ga, In)
▪ Make it N type by injecting elements from type-V (P,As)
▪ You can control the amount of doping
▪ Highly doped (i.e. p++, n+), lightly doped (i.e. p-)
▪ Doping concentration 1015 .. 1020, a fraction of Avogadro’s number
▪ You can generate P and N regions (pn junctions) next to each other
▪ Allows you to make interesting electrical devices
▪ Diodes, transistors, thyristors..

VLSI 2: From Netlist to Complete System on Chip 10

Remember the transistor

VLSI 2: From Netlist to Complete System on Chip 11

Let’s take a look
For 30+ years the gate was NOT metal
but polysilicon!

conductor
(gate) M
P olysilicon
etal

dielectric O xide

n doped region
(drain) S p doped region
emiconductor
(source)

p doped silicon wafer (semiconductor substrate)

VLSI 2: From Netlist to Complete System on Chip 12

Moore’s Law wants to shrink this structure

conductor
(gate)

dielectric

n doped region p doped region

(drain) (source)

p doped silicon wafer (semiconductor substrate)

VLSI 2: From Netlist to Complete System on Chip 13

 Moore’s Law wants to shrink this structure

Patterning smaller structures

Atomistic sizes, variation

gate
dielectric
drain source

Shrinking oxide, higher E field

p doped silicon wafer (semiconductor substrate)

VLSI 2: From Netlist to Complete System on Chip 14

 You also need to access these structures
Patterning dense structures

Digging small holes Filling small holes

gate
dielectric
drain source

p doped silicon wafer (semiconductor substrate)

VLSI 2: From Netlist to Complete System on Chip 15

Finding compatible materials is an issue!
▪ Silicon processing is quite complex
▪ Many layers, many materials, process steps
▪ All materials need to be (somewhat) compatible
▪ Stick to each other
▪ Have similar thermal expansion co-efficients
▪ Be compatible with the other processing steps
▪ The processing should not have adverse effects
▪ Rely on dangerous materials
▪ Spiking, contamination
▪ Some choices are due to such considerations
▪ For example Wolfram for contacts/vias
Picture from https://commons.wikimedia.org/wiki/File:Gluehlampe_01_KMJ.png by KMJ

VLSI 2: From Netlist to Complete System on Chip 16

Patterning the surface using lithography
▪ The desired pattern on mask
▪ Features 5x-10x larger
▪ Etched on a metallic surface
▪ Optics used to focus on surface
▪ Size reduced to the actual dimensions
▪ Only a fraction of the surface illuminated
▪ The wafer is ’stepped’
▪ Moved so that next area can be patterned
▪ Can cover the entire wafer

Optics only work up to 193nm

VLSI 2: From Netlist to Complete System on Chip 17
Basic steps of processing: adding photoresist
▪ Coat photoresist
▪ Usually organic material
▪ Needs to be cured
▪ Is sensitive to certain light

Photoresist

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 18

Basic steps of processing: exposing patterns
▪ Coat photoresist
▪ Illuminate through mask
▪ The pattern of the mask is reflected
the on surface Illumination
▪ Exposed resist changes property

Photoresist

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 19

Basic steps of processing: developing photoresist
▪ Coat photoresist
▪ Illuminate through mask
▪ Develop photoresist
▪ Cure resist so that it can be
removed/kept through solvent
▪ Remove cured (positive) part
or non-cured (negative) part

Photoresist

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 20

Basic steps of processing, manufacturing
▪ Coat photoresist
▪ Illuminate through mask
▪ Develop photoresist
▪ Apply manufacturing step
▪ Etching, Deposition, Implantation
▪ Photoresist will protect surface
▪ Exposed area will get processed
Photoresist

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 21

Basic steps of processing, next steps
▪ Coat photoresist
▪ Illuminate through mask
▪ Develop photoresist
▪ Apply manufacturing step
▪ Remove resist
▪ Organic material, can be dissolved
▪ Washed and cleaned

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 22

Basic steps of processing, next steps
▪ Coat photoresist
▪ Illuminate through mask Align next mask to the same position
▪ Develop photoresist
▪ Apply manufacturing step Surface is straight enough to pattern
▪ Remove resist
▪ Rinse and repeat
▪ Process will take 100 of steps
▪ 10s of masks

Surface of wafer

VLSI 2: From Netlist to Complete System on Chip 23

Masks a summary

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2: From Gate-Level Circuits to CMOS Fabrication”

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The big innovation nMOS + pMOS == CMOS

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2: From Gate-Level Circuits to CMOS Fabrication”
VLSI 2: From Netlist to Complete System on Chip 25
Logical vs Physical masks
▪ We draw masks for regions

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
▪ Gate
▪ Active
▪ N-Well etc

From Gate-Level Circuits to CMOS Fabrication”

▪ During manufacturing some
can be derived from others
▪ Physical masks are manufactured
▪ Same mask can be used for
different steps
▪ Saves costs

VLSI 2: From Netlist to Complete System on Chip 26

Step by step (on the blackboard, simplified)

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2: From Gate-Level Circuits to CMOS Fabrication”

VLSI 2: From Netlist to Complete System on Chip 27

 Forming the wells

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
28

From Gate-Level Circuits to CMOS Fabrication”

 Active areas

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
29

From Gate-Level Circuits to CMOS Fabrication”

 Transistors

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
30

From Gate-Level Circuits to CMOS Fabrication”

 Contacts

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
31

From Gate-Level Circuits to CMOS Fabrication”

 Metal1

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
32

From Gate-Level Circuits to CMOS Fabrication”

 Higher metals

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2:
33

From Gate-Level Circuits to CMOS Fabrication”

Once again the final state

Slide adapted from Hubert Kaeslin, “Top-Down Digital VLSI Design Vol2: From Gate-Level Circuits to CMOS Fabrication”

VLSI 2: From Netlist to Complete System on Chip 36

 ICT
Interconnect technology file

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The metal stack determines parasitic effects
▪ ICT file (or similar) captures the metal stack
▪ Lists which materials are used with their resistivity, permittivity values
▪ Includes also height of the materials allows to re-construct the stack
▪ Used to construct tables to extract
▪ Resistance of wires and vias/contacts
▪ Capacitance between wires
▪ Not a common file these days
▪ Modern manufacturing is very complex, multiple smaller layers used
▪ Detailed description could reveal technology secrets
▪ Companies deliver ‘already extracted tables for RC ’ for parasitics instead

VLSI 2: From Netlist to Complete System on Chip 38

Anatomy of an ICT file
// […] Adapted/simplified example
conductor "Polysilicon" {
height 0.600
thickness 0.15
resistivity 7
Conformal: follows contours
layer_type gate of lower layer
gate_forming_layer true
temp_tc1 0.0029
} Usually multiple layers for
// […]
dielectric ”ox1" {
dielectric needed
conformal FALSE
height 0.750
thickness 0.50 Quite rare these days
dielectric_constant 4.1
}
}
VLSI 2: From Netlist to Complete System on Chip 39
Next steps
▪ Exercise: Synthesis
▪ We will make use what we learned last week in the exercise
▪ Use Yosys to synthesize Croc into a gate-level netlist

▪ Next Lecture: Physical design

▪ Standard cells
▪ Memory macros
▪ Layers for routing
▪ Components and know-how to start building our chip

VLSI 2: From Netlist to Complete System on Chip 40