A1220 1 2 3 Datasheet
A1220 1 2 3 Datasheet
VCC
Regulator
To All Subcircuits
Low-Pass VOUT
Sample and Hold
Filter
Dynamic Offset
Cancellation
Amp Control
Current Limit
GND
DESCRIPTION (continued)
external resistance in series with the supply pin for greater protection
against high voltage transient events.
Two package styles provide magnetically optimized packages for
most applications. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultra-mini SIP for RoHS
through-hole mounting. Both packages are lead (Pb) free, with 100%
COMPLIANT
matte-tin-plated leadframes.
SELECTION GUIDE
Part Number Packing [1] Mounting Ambient, TA BRP (Min) BOP (Max)
A1220ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1220ELHLT-T [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40°C to 85°C
A1220EUA-T [3] Bulk, 500 pieces/bag 3-pin SIP through hole
–40 G 40 G
A1220LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1220LLHLT-T [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C
A1220LUA-T [3] Bulk, 500 pieces/bag 3-pin SIP through hole
A1221ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1221ELHLT-T [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40°C to 85°C
A1221EUA-T [3] Bulk, 500 pieces/bag 3-pin SIP through hole
–90 G 90 G
A1221LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1221LLHLT-T [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C
A1221LUA-T [3] Bulk, 500 pieces/bag 3-pin SIP through hole
A1222ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1222ELHLX-T [2] 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 85°C
A1222EUA-T [4] Bulk, 500 pieces/bag 3-pin SIP through hole
–150 G 150 G
A1222LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1222LLHLX-T [2] 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C
A1222LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1223ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1223ELHLX-T [2] 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 85°C
A1223EUA-T [4] Bulk, 500 pieces/bag 3-pin SIP through hole
–180 G 180 G
A1223LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1223LLHLX-T [2] 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C
A1223LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
[1] Thisrating does not apply to extremely short voltage transients such as Load Dump and/or ESD. Those events have individual
ratings, specific to the respective transient voltage event.
Package LH Package UA
1 2 3
1 2
VCC
VOUT
GND
VCC
VOUT
Terminal List
Number
Name Description
Package LH Package UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. [1] Max. Unit [2]
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage VCC Operating, TJ < 165°C 3 – 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP – – 10 µA
Output Saturation Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 185 500 mV
Output Current Limit IOM B > BOP 30 – 60 mA
VCC > 3.0 V, B < BRP(min) – 10 G,
Power-On Time [3] tPO – – 25 µs
B > BOP(max) + 10 G
Chopping Frequency fC – 800 – kHz
Output Rise Time [3][4] tr RL = 820 Ω, CL = 20 pF – 0.2 2 µs
Output Fall Time [3][4] tf RL = 820 Ω, CL = 20 pF – 0.1 2 µs
ICC(ON) B > BOP, VCC = 12 V – – 4 mA
Supply Current
ICC(OFF) B < BRP, VCC = 12 V – – 4 mA
Reverse Supply Current IRCC VRCC = –20 V – – –5 mA
Supply Zener Clamp Voltage VZ ICC = 5 mA; TA = 25°C 28 – – V
Zener Impedance IZ ICC = 5 mA; TA = 25°C – 50 – Ω
MAGNETIC CHARACTERISTICS
A1220 5 22 40 G
A1221 15 50 90 G
Operate Point BOP
A1222 70 110 150 G
A1223 100 150 180 G
A1220 –40 –23 –5 G
A1221 –90 –50 –15 G
Release Point BRP
A1222 –150 –110 –70 G
A1223 –180 –150 –100 G
A1220 10 45 80 G
A1221 30 100 180 G
Hysteresis BHYS (BOP – BRP)
A1222 140 220 300 G
A1223 200 300 360 G
[1] Typical
data are are at TA = 25°C and VCC = 12 V, and are for initial design estimations only.
[2] 1G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] C = oscilloscope probe capacitance.
L
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
Package Thermal Resistance RθJA 110 °C/W
connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
21
20
19
18
17
16
15
14
13
12
Package LH, 2-layer PCB
11 (RθJA = 110 ºC/W)
10
9 Package UA, 1-layer PCB
8 (RθJA = 165 ºC/W)
7
6 Package LH, 1-layer PCB
5 (RθJA = 228 ºC/W)
4
3 VCC(min)
2
20 40 60 80 100 120 140 160 180
Temperature (ºC)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (mW)
1200 Pa
1100 (R cka
θJ ge
A = L
1000 11 H, 2
Pac 0 º -la
900 C/ ye
800 (R kage W
) r PC
θJA = UA B
165 1-la,
700 ºC/ yer
W) PC
600 B
500 Pac
k
400 (R age LH
,
300 θJA =
228 1-laye
ºC/W r PC
200 ) B
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
CHARACTERISTIC PERFORMANCE
A1220, A1221, A1222, and A1223 Electrical Characteristics
Average Supply Current (On) versus Temperature Average Supply Current (On) versus Supply Voltage
6.0 6.0
5.5 5.5
5.0 5.0
4.5 3.0V 4.5
4.0 3.8V 4.0
ICC(AV) (mA)
Icc(AV)(mA)
3.5 4.2V 3.5 150°C
3.0 12V 3.0 25°C
-40°C
2.5 24V 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
Average Supply Current (Off) versus Temperature Average Supply Current (Off) versus Supply Voltage
6.0 6.0
5.5 5.5
5.0 5.0
4.5 4.5
4.0 4.0
ICC(AV) (mA)
3.0V
Icc(AV)(mA)
250 250
2.6V
200 200
VOUT(SAT) (mV)
150°C
VOUT(SAT) (mV)
3.0V
25°C
3.8V -40°C
150 150
4.2V
12V
100 100
24V
50 50
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 2 4 6 8 10 12 14 16 18 20 22 24 26
TA (°C) VCC (V)
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
35 35
(V)
30 30
3.0
(°C)
25 3.8 25
-40
BOP (G)
BOP (G)
4.2 25
20 20
12 150
15 24 15
10 10
5 5
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
-5 -5
-10 -10
(V)
-15 -15 (°C)
3.0
BRP (G)
BRP (G)
-40
-20 3.8 -20 25
4.2 150
-25 12 -25
24
-30 -30
-35 -35
-40 -40
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
BHYS (G)
45 3.0 45
40 40 -40
3.8
35 35 25
4.2 150
30 30
25 12 25
20 24 20
15 15
10 10
5 5
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
BOP (G)
BOP (G)
50 50 -40
2.6
40 12 40 25
24 150
30 30
20 20
10 10
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
BHYS (G)
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
BOP (G)
BOP (G)
130 -40
110 2.6
24 120 25
100 110 150
100
90
90
80 80
70 70
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
-120 -40
-110 2.6
-130 25
24
-120 150
-140
-130 -150
-160
-140 -170
-150 -180
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
280 280
260 260
BHYS (G)
-40
220 2.6 220 25
24
150
200 200
180 180
160 160
140 140
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
FUNCTIONAL DESCRIPTION
OPERATION APPLICATIONS
The output of these devices switches low (turns on) when a mag-
It is strongly recommended that an external bypass capacitor be
netic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see panel A of figure 1). After turn-on, the connected (in close proximity to the Hall element) between the
output voltage is VOUT(SAT) . The output transistor is capable of supply and ground of the device to reduce both external noise
sinking current up to the short circuit current limit, IOM, which is and noise generated by the chopper stabilization technique. As is
a minimum of 30 mA. When the magnetic field is reduced below shown in panel B of figure 1, a 0.1 µF capacitor is typical.
the release point, BRP , the device output goes high (turns off).
Extensive applications information for Hall-effect devices is
The difference in the magnetic operate and release points is the
available in:
hysteresis, BHYS , of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external • Hall-Effect IC Applications Guide, Application Note 27701
mechanical vibration and electrical noise.
• Guidelines for Designing Subassemblies Using Hall-Effect
Removal of the magnetic field will leave the device output Devices, Application Note 27703.1
latched on if the last crossed switch point is BOP, or latched off if
the last crossed switch point is BRP. • Soldering Methods for Allegro’s Products – SMT and Through-
Hole, Application Note 26009
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an indeterminate output state. The cor- All are provided in Allegro Electronic Data Book, AMS-702, and
rect state is attained after the first excursion beyond BOP or BRP . the Allegro website, www.allegromicro.com.
VS
V+
VCC
Switch to High
Switch to Low
VCC RL
VOUT
A122x
CBYP
VOUT
0.1 µF
Output
VOUT(SAT) GND
0
B– 0 B+
BOP
BRP
BHYS
(A) (B)
Figure 1. Switching behavior of latches. In panel A, on the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength,
and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited
when using a circuit such as that shown in panel B.
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
CHOPPER STABILIZATION TECHNIQUE The chopper stabilization technique uses a 400 kHz high fre-
When using Hall effect technology, a limiting factor for switch quency clock. For demodulation process, a sample and hold
point accuracy is the small signal voltage developed across the technique is used, where the sampling is performed at twice the
Hall element. This voltage is disproportionally small relative to chopper frequency (800 kHz). This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
the offset that can be produced at the output of the Hall element.
and faster signal-processing capability. This approach desensi-
This makes it difficult to process the signal while maintaining an
tizes the chip to the effects of thermal and mechanical stresses,
accurate, reliable output over the specified operating temperature and produces devices that have extremely stable quiescent Hall
and voltage ranges. output voltages and precise recoverability after temperature
Chopper stabilization is a unique approach used to minimize cycling. This technique is made possible through the use of a
Hall offset on the chip. The Allegro technique, namely Dynamic BiCMOS process, which allows the use of low-offset, low-noise
amplifiers in combination with high-density logic integration and
Quadrature Offset Cancellation, removes key sources of the out-
sample-and-hold circuits.
put drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodula- The repeatability of magnetic field-induced switching is affected
tion process. The undesired offset signal is separated from the slightly by a chopper technique. However, the Allegro high
magnetic field-induced signal in the frequency domain, through frequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that are
modulation. The subsequent demodulation acts as a modulation
more likely to be sensitive to such degradation are those requiring
process for the offset, causing the magnetic field induced signal precise sensing of alternating magnetic fields; for example, speed
to recover its original spectrum at baseband, while the dc offset sensing of ring-magnet targets. For such applications, Allegro
becomes a high-frequency signal. The magnetic sourced signal recommends its digital device families with lower sensitivity
then can pass through a low-pass filter, while the modulated DC to jitter. For more information on those devices, contact your
offset is suppressed. This configuration is illustrated in figure 2. Allegro sales representative.
Regulator
Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold
Amp
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
POWER DERATING Example: Reliability for VCC at TA = 150°C, package LH, using a
The device must be operated below the maximum junction minimum-K PCB.
temperature of the device, TJ(max). Under certain combinations of
Observe the worst-case ratings for the device, specifically:
peak conditions, reliable operation may require derating supplied
RθJA = 228°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
power or improving the heat dissipation properties of the appli-
ICC(max) = 4 mA.
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the Calculate the maximum allowable power level, PD(max). First,
Allegro MicroSystems website.) invert equation 3:
The Package Thermal Resistance, RθJA, is a figure of merit sum- ΔTmax = TJ(max) – TA = 165°C – 150°C = 15°C
marizing the ability of the application and the device to dissipate
This provides the allowable increase to TJ resulting from internal
heat from the junction (die), through all paths to the ambient air.
power dissipation. Then, invert equation 2:
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces. PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 228°C/W = 66 mW
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air Finally, invert equation 1 with respect to voltage:
motion are significant external factors, damped by overmolding. VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 4 mA = 16.4 V
The effect of varying power levels (Power Dissipation, PD), can The result indicates that, at TA, the application and device can
be estimated. The following formulas represent the fundamental dissipate adequate amounts of heat at voltages ≤VCC(est).
relationships used to estimate TJ, at PD.
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
PD = VIN × IIN (1) able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
ΔT = PD × RθJA (2) VCC(max) is reliable under these conditions.
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 1.6 mA, and RθJA = 165°C/W, then:
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
+0.125
2.975 –0.075
1.49
4°±4°
3 Active Area Depth
0.28 ±0.04 mm
+0.020
0.180–0.053
2.40
0.96 0.70
+0.10 +0.19
2.90 –0.20 1.91 –0.06
0.95
1 2
PCB Layout Reference View
0.55 REF 0.25 BSC All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
Seating Plane to meet application process requirements and PCB layout tolerances
Gauge Plane
0.57 ±0.04
3× 1.00 ±0.13 C XXT
0.10 C 0.41 ±0.04
SEATING
PLANE
+0.10 1
0.05 –0.05
Standard Branding Reference View 1
0.95 BSC
0.40 ±0.10
Line 1 = 3 characters
XXX
1
Standard Branding Reference View 2
Line 1 = 3 characters
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
XXX
45° (2×) 1.52 ±0.05 1.68 MAX
0.10 MAX
5° (2×) 1
0.51 REF
0.05 NOM
0.05 NOM
0.10 MAX
0.10 MAX
Dambar Trim Detail
14
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
+0.08 Pin Indent NNT
3.02 –0.05
E
Branded 45°
Face 1
2.16 D Standard Branding Reference View
MAX
= Supplier emblem
0.79 REF N = Last two digits of device part number
NOT FOR
A T = Temperature code
0.51
REF
NEW DESIGN
1 2 3
15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1220, A1221,
A1222, and A1223 Chopper-Stabilized Precision Hall-Effect Latches
Revision History
Number Date Description
15 September 16, 2013 Update UA package drawing
16 September 21, 2015 Added AEC-Q100 qualification under Features and Benefits
17 January 12, 2016 Updated Reverse Supply Current test conditions in Electrical Characteristics table
18 October 20, 2016 Chopper-style UA package designated as not for new design
Updated Maximum Junction Temperature in Absolute Maximum Ratings table and
19 September 22, 2017
Figure 1B; added Functional Safety information
20 October 12, 2018 Minor editorial updates
21 November 21, 2019 Minor editorial updates
Removed ASIL logos and references; added typical applications (page 1); updated
22 February 18, 2021
package drawing reference number (page 13)
23 February 15, 2022 Updated package drawings (pages 13-14)
24 September 30, 2024 Updated part variants A1222EUA-T and A1223EUA-T to last-time buy status
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com