UNIT - IV

1. CPU Control Unit Design

 Contents
• Hardwired and micro-programmed design
approach

REFERENCES:
1. “Computer System Architecture”, by M. Morris Mano, 3rd
Edition
 (For Reference)

Fig: Basic Functional units of a Computer

• Function of the control unit
– is to initiate sequences of MICROOPERATIONS

• There are four categories of the most common

microoperations:

– Register transfer: transfer binary information from one

register to another

– Arithmetic: perform arithmetic operations on numeric

data stored in registers

– Logic: perform bit manipulation operations on non-

numeric data stored in registers

– Shift: perform shift operations on data stored in registers

The Computer: Top-Level Structure (For Reference)
Q:

A:
A:

Different

Control function that specifies a

microoperation is a binary variable.
When it is in one binary state, the
corresponding microoperation is executed.
• The ‘+’ sign has two different meanings:
– logical OR and summation
• When + is in a microoperation, then
summation
• When + is in a control function, then OR
• Example:
P + Q: R1  R2 + R3, R4  R5 V R6
control function -- P + Q -- OR operation
microoperation -- R2 + R3 -- Add Microoperation
microoperation -- R5 V R6 -- OR operation
• Methods for implementing CONTROL UNIT:
– HARDWIRED control
– MICRO-PROGRAMMED control

• In Hardwired control organization,

– Design involves the use of fixed instructions, fixed logic blocks of
and/or arrays (gates, flip-flops), encoders, decoders, and other
digital circuits.

– Few CPUs with hardwired logic control Intel 8085, Motorola 6802,
Zilog 80, and any RISC CPUs.

– Key Characteristics: high-speed operation, expensive, relatively

complex, no flexibility in adding new instructions.

– If the design has to be modified or changed, It requires changes in

the wiring among the various components.
 Hardwired Control Unit for the basic computer

Instruction Register (IR)

CU consists of 15 14 13 12 11 - 0 Other inputs

•Two decoders 3x8

decoder
7 6543 210
•A sequence counter D0
I Control
D7 Control
•No.of control logic gates logic outputs
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
• Inputs to the control unit come from IR (an instruction
read from the memory)

• A hardwired control is implemented in basic computer

using:
– A 3 X 8 decoder to decode opcode bits 12-14 into signals D0, ...,
D7
– A 4-bit binary sequence counter (SC) to count from 0 to 15 to
achieve time sequencing
– A 4 X 16 decoder to decode the output of the counter into 16
timing signals, T0, ..., T15
– A flip-flop (I) to store the addressing mode bit in IR

• A digital circuit (Control Logic gates) with

– Inputs : D0, ..., D7, T0, ..., T15, I, and address bits (11-0) in IR—
to generate control outputs supplied to control inputs and
select signals of the registers and the bus
• Clocking principle:

– 4-bit binary sequence counter goes through a cycle, 0000

→ 0001 → 0010 → ...... → 1111 → 0000 to provide
sequence of timing signals T0 → T1 → T2 → ... → T15 →
T0 out of the 4 X 16 decoder

– Accordingly only one of T0, T1 ....., T14, T15 is ‘1’ at each

clock cycle and all the other timing signals are ‘0’

– By setting the clear input (CLR) of SC at a clock cycle, say

T3, we can achieve a 4- cycle clock: T0 → T1 → T2 → T3
→ T0
•Example:- Timing diagram for the statement
D3T4: SC  0 is given below
•Sequence Counter (SC) responds (increments) to positive
transition of clock ( 0000 to 1111 produces one of T0 to T15 as
o/p of decoder)
• At time T4, SC is cleared to ‘0’ if decoder output D3 is active.
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Fig: Example of control timing Signals

• In the Hardwired organization,
– control logic is implemented with gates, flip-flops,
decoders, and other digital circuits
– Adv: produces fast mode operation
– Disadv: requires changes in the wiring among
various components if design has to be modified

• In the Microprogrammed organization,

– control information is stored in a control memory
– control memory is programmed to initiate the
required sequence of microoperations
– Adv: Microprogram in control memory has to be
updated, if design has to be modified
 Microprogrammed control organization
• Control Address Register
– specifies the address of the microinstruction

• Control memory
– is assumed to be a ROM, within which all control information is permanently stored
– Control memory is programmed to initiate the required sequence of microoperations.

• Control Data Register

– holds the Microinstruction read from Memory

• Next Address
– must be determined, after these operations are executed
– may Also be a function of external input conditions

Figure: Microprogrammed control organization

 Control Memory
• CONTROL MEMORY
– is a memory that is part of a control unit
– can be a read-only memory (ROM)
– But Dynamic microprogramming (writable control memory)
• permits a MICROPROGRAM to be loaded initially from an auxiliary
memory such as a magnetic disk

• MICROPROGRAM is
– a sequence of microinstructions
– Principle of microprogramming is systematic method for
controlling the microoperation sequences in a digital computer

• MICROINSTRUCTION
– Each word in control memory contains within it a microinstruction

• CONTROL WORD
– is control variable represented by a string of 1's and 0‘s
 TABLE:
Symbolic Microprogram
(Partial)

(For ILLUSTRATION)

Figure: MICROINSTRUCTION CODE FORMAT

(20 bits)

(Microinstruction-1)
(Microinstruction-2)
(Microinstruction-3)
• A computer that employs a microprogrammed
control unit will have two separate memories:
– Main memory
– Control memory

• Main memory
– is available to the user for storing the programs.
– contents may alter when the data are manipulated
– user's program in it consists of machine
instructions and data
• Control Memory Address
0 0000 00 ADD Routine

– holds a fixed Microprogram 0 0001 00 AND Routine

(Ex:-FETCH, ADD)
0 0010 00 LDA Routine

– can NOT be altered by the occasional user 0 0011 00 STA Routine

0 0100 00
– consists of Microinstructions (Ex:- PCTAR) BUN Routine

• that specify various internal control signals

for execution of register microoperations Control
Memory

– Each MACHINE INSTRUCTION initiates a series of

MICROINSTRUCTIONS in control memory

– These MICROINSTRUCTIONS generate the MICROOPERATIONS

• to fetch the instruction from main memory
• to evaluate the effective address
• to execute the operation specified by the instruction
• to return control to the fetch phase in order to repeat the cycle for the
next instruction
• Next address generator is sometimes called a MICROPROGRAM
SEQUENCER
– it determines the address sequence that is read from control
memory

• Typical functions of a Microprogram sequencer are

– incrementing the Control Address Register (CAR) by one
– loading into the CAR an address
– transferring an external address, or loading an initial address to start
the control operations

Figure: Microprogrammed control organization

• System can operate without the control data register by
applying a single-phase clock to the address register

• Control word and next-address information are taken

directly from the control memory

• ROM (Control Memory) operates as a Combinational

Circuit, with the address value as the input and the
corresponding word as the output

• In the example, assume a single-phase clock,

– Only Address Register receives clock pulses
– So NO need to use a Control Data Register
– Sequencer and Control Memory do NOT need a clock as
those are combinational circuits
• Main advantage of the microprogrammed control is

– once the hardware configuration is established, there

should be NO NEED for further HARDWARE or WIRING
CHANGES

– If we want to establish a different control sequence for

the system, all we need to do is specify a DIFFERENT SET
OF MICROINSTRUCTIONS (MICROPROGRAM) in control
memory
 Address Sequencing
• Routine
– is a group of Microinstructions stored in control memory

• Each COMPUTER INSTRUCTION has its OWN MICROPROGRAM

ROUTINE (a sequence of microinstructions) in control memory

• Address sequencing capabilities required in a control

memory are:
1. Incrementing of the Control Address Register (CAR)
2. Unconditional Branch or Conditional Branch, depending on
status bit conditions
3. A Mapping Process from the bits of the instruction to an
address for control memory
4. A facility for subroutine call and return
Figure shows a block diagram of
SELECTING the NEXT
MICROINSTRUCTION ADDRESS

CONTROL ADDRESS REGISTER (CAR)

receives the address from FOUR
DIFFERENT PATHS

• INCREMENTER increments the

content of the Control Address
Register (CAR) by one

• BRANCHING is achieved by
specifying the branch address in
one of the fields of the
microinstruction
– Conditional branching depends
on specific status bit in order to
determine its condition

• EXTERNAL ADDRESS is
transferred into control memory
via a MAPPING Logic Circuit

• RETURN ADDRESS for a

subroutine is stored in a
Subroutine Register (SBR)

Figure: Selection of address for control memory

 Conditional Branching
• Status Conditions are special bits in the system that provide parameter information
such as
– carry-out of an adder
– sign bit of a number
– mode bits of an instruction
– input or output status conditions

• Branch address is specified by status bits, together with the field in the
microinstruction

• Branch Logic provides decision-making capabilities in the control unit

(For Reference)

Figure: MICROINSTRUCTION CODE FORMAT

(20 bits)
• Branch Logic hardware may be implemented in a variety of
ways
– Test the specified condition and branch to the indicated
address if the condition is met;
– otherwise, the address register is incremented
– This can be implemented with a Multiplexer

• For Example, there are EIGHT status bit CONDITIONS in the

system
– Three bits (select bits) in the microinstruction are used to
specify any one of eight status bit conditions
– If the selected status bit is in the 1 state, multiplexer transfer
the branch address into CAR
– Otherwise, it is 0, multiplexer causes the address register to be
incremented

• An UNCONDITIONAL branch microinstruction loads the

branch address into the CAR from control memory
 Mapping of Instruction
• For example (Fig.),
– A computer instruction has an operation code of 4 bits ( specifies 16
instructions)
– Assume Control Memory has 128 words (requires address of 7 bits)
• For each OPERATION CODE there exists a MICROPROGRAM ROUTINE in
control memory

• One simple MAPPING PROCESS that converts the 4-BIT OPERATION CODE to
a 7-BIT ADDRESS for CONTROL MEMORY is shown in Fig.
– This mapping consists of placing a 0 in the Most Significant Bit of the address,
– transferring the four operation code bits, and clearing the two Least Significant
Bits of the Control Address Register
• This provides for each COMPUTER INSTRUCTION a MICROPROGRAM
ROUTINE with a capacity of FOUR MICROINSTRUCTIONS

Fig.: Mapping from

INSTRUCTION CODE to
MICROINSTRUCTION ADDRESS
 MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions
ADD 0000
AND 0001
LDA 0010
STA 0011
BUN 0100

Mapping
Bits 0 xxxx 00 Address
0 0000 00 ADD Routine

0 0001 00 AND Routine

0 0010 00 LDA Routine

0 0011 00 STA Routine

0 0100 00 BUN Routine

Control
Memory
 Microprogram Example
Computer Configuration
• The block diagram of the MUX
computer configuration is
10 0
shown in Fig.
AR
Address Memory
• It consists of two memory 10 0
2048 x 16
units:
PC
– a main memory for
storing instructions and
data
– a control memory for MUX
storing the microprogram
15 0
6 0 6 0
• Four registers (AR, PC, DR, DR
SBR CAR
AC)are associated with the
Processor Unit
Control memory Arithmetic
• Two with the control unit 128 x 20 logic and
– Control Address Register shift unit
(CAR) Control unit
– a subroutine register 15 0
(SBR) AC

Figure: Computer Hardware Configuration

Subroutines
• Microprograms that use subroutines must have a
provision for storing the RETURN address

• This may be accomplished by placing the

incremented output from the CAR into a subroutine
register and branching to beginning of the
subroutine

• The best way to structure a register file that stores

addresses for subroutines is to organize the
registers in a last-in, first-out (LIFO) stack
• Fig (a) depicts COMPUTER INSTRUCTION format
• Fig (b) lists FOUR of the 16 possible Memory-Reference instructions
• each Computer Instruction must be Microprogrammed

Memory
2048 x 16

Figure: COMPUTER INSTRUCTIONS

• Transfer of information among
the registers in the processor is
done through MULTIPLEXERS
rather than a common bus MUX
– DR can receive information from 10 0
AC, PC, or Memory AR
– AR can receive information from Address Memory
PC or DR 2048 x 16
10 0
– PC can receive information only PC
from AR

• Arithmetic logic and shift unit

(ALU) performs microoperations MUX
with data from AC and DR and
places the result in AC 15 0
6 0 6 0
DR
SBR CAR
• Memory receives its address
from AR Control memory Arithmetic
– Input data written to memory 128 x 20 logic and
come from DR shift unit
– Data read from memory can go Control unit
only to DR 15 0
AC

Figure: Computer Hardware Configuration

Microinstruction Format
• Microinstruction format for the Control Memory is shown in Fig.
• Microinstruction contains 20 bits
• These are divided into FOUR functional parts
• Microoperation Field
– Further divided into three fields F1, F2, and F3
• CD field Control memory
128 x 20
– selects status bit conditions
• BR field
– specifies the type of branch to be used
• AD field
– contains a branch address
– It is 7 bits wide, since the control memory has 128 = 2 7 words

Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

• Microoperations are sub-divided into
three fields of three bits each (F1,F2,F3)

• Three bits in each field are encoded to

specify 7 distinct microoperations (listed
in Table)

TABLE: Symbols and Binary Code

for MICROINSTRUCTION fields
• Assume, (For Reference)
– MAP microinstruction at the end of
the FETCH routine caused a branch
to address ‘0’
– ADD routine is stored in address ‘0’
ADD Routine
• First microinstruction in the ADD
routine CALLS subroutine INDRCT,
conditioned on status bit ‘I’
– If I = 1, a branch to INDRCT occurs
– and RETURN address (address 1 in
this case) is stored in the subroutine
register SBR
– INDRCT subroutine has two
microinstructions:

– Memory has to be accessed (READ)

to get the Effective Address
– then transferred to AR (DRTAR)
– Return from subroutine (RET)
transfers the address from SBR to
CAR
• Thus returning to the Second
microinstruction of the ADD routine
• This gives a total of 21 microoperations (7 from each field (F1,F2,F3))
• NO more than 3 microoperations can be chosen for one Microinstruction

Example:
• A microinstruction can specify two simultaneous microoperations from
F2 and F3 and none from F1

• Nine bits of the microoperation fields will then be

000 100 101 (F1 F2 F3)
• Two or more conflicting microoperations CANNOT be specified
simultaneously
For example,
– a microoperation field 010 001 000 has NO MEANING
AC0 (F1) ACAC-DR (F2) NOP
– because it specifies the operations to clear AC to 0 and subtract DR from AC
at the same time
• TRANSFER-TYPE microoperations
symbols use FIVE letters
– First Two Letters designate the
Source Register
– Third Letter is always a ‘T’
– Last Two Letters designate the
Destination Register

For example,
– microoperation that specifies the
transfer
AC  DR (F1 = 100)
– has the symbol DRTAC, which
stands for a transfer from DR to AC
• CD (Condition) field consists of TWO bits
• These bits are encoded to specify FOUR Status Bit Conditions (as listed in
Table)
– U,I,S and Z
• First condition is always a 1
– So, CD = 00 (symbol U) will always find the condition to be TRUE
– In conjunction with BR (branch) field, it provides an UNCONDITIONAL BRANCH
operation
• Indirect bit ‘I’ (bit 15 of DR) after an instruction is read from memory
• Sign bit of AC (bit 15 of AC) provides the next status bit
• Zero value ‘Z’ is a binary variable whose value
– is equal to 1 if all the bits in AC = 0

Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

• BR (Branch) field consists of TWO bits
• It is used, in conjunction with the address field AD, to choose the address of
the next microinstruction
– When BR = 00, the control performs a jump (JMP) operation (which is similar to a
branch)
– When BR = 01, it performs a call to subroutine (CALL) operation
• Two operations are identical except that
– a CALL microinstruction stores the RETURN address in the Subroutine Register
(SBR)
• JUMP and CALL operations depend on the value of the CD field
– If CD = 01 (indirect address bit), the next address in the AD field is transferred to
the Control Address Register (CAR)
– Otherwise, CAR is incremented by 1

Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

• RETURN from subroutine is accomplished with a BR = 10
– This causes the transfer of the return address from SBR to CAR

• MAPPING from the operation code bits of the instruction

to an address for CAR is accomplished when the BR = 11

• Last two conditions in the BR field are independent of the

values in the CD and AD fields

Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

Symbolic Microinstructions

• Each line of the Assembly Language Microprogram

defines a symbolic microinstruction

• A Symbolic Microprogram can be translated into its

binary equivalent by means of an ASSEMBLER

• Each Symbolic Microinstruction is divided into FIVE

fields:
– Label, Microoperations, CD, BR, AD
 • LABEL field
– may be empty or it may specify a symbolic address
– A label is terminated with a colon (:)
• Microoperations field
– consists of one or two or three symbols, separated by commas
• CD field
– has one of the letters U, I, S, or Z
• BR field
– contains one of the four symbols (JMP, CALL, RET, MAP)

Example:
• AD field specifies a value for the address field of the
microinstruction in one of three possible ways:
a. With a symbolic address, which must also appear as a LABEL (INDRCT)
b. With the symbol NEXT to designate the next address in sequence
c. When the BR field contains a RET or MAP symbol,
-- the AD field is left EMPTY and is converted to seven zeros by the
assembler

• ORG is a PSEUDOINSTRUCTION to define the ORIGIN, or FIRST

ADDRESS (here 64), of a Microprogram Routine (FETCH)
– Ex:- symbol ORG 64 informs the assembler to place the next
microinstruction in control memory at decimal address 64 (binary
address 1000000)
Example:
The Fetch Routine
• Control Memory has 128 words, and each word contains 20 bits
• To Microprogram the control memory,
– First 64 words (addresses 0 to 63) are to be occupied by the Routines for
the 16 instructions (EX:- ADD, BRANCH, STORE, EXCHANGE)
– Last 64 words (addresses 64 to 127) may be used for Other purpose (EX:-
FETCH, INDRCT)
• A convenient starting location for the FETCH routine is address 64

• MICROINSTRUCTIONS needed for the FETCH Routine are:

(Microinstruction-1)
(Microinstruction-2)
(Microinstruction-3)

• FETCH routine needs THREE MICROINSTRUCTIONS, which are placed in

control memory at addresses 64, 65, and 66

• Using the assembly language conventions, write the SYMBOLIC

MICROPROGRAM for the FETCH routine as follows:

(64)
(65)
(66)

• Translation of the symbolic microprogram to BINARY produces the

following BINARY MICROPROGRAM:

(64)
. (65)
(66)
TABLE: Symbols and Binary Code
for MICROINSTRUCTION fields
Symbolic MICROPROGRAM

• Several MICROINSTRUCTIONS in each routine

– for evaluating the effective address
– for executing the instruction

• If the microinstructions for the indirect address are

stored as a subroutine
– it is symbolized by INDRCT
– and is located after fetch routine, (shown in Below Table)

• Below table shows the symbolic microprogram for the

fetch routine and the microinstruction routines that
execute FOUR computer instructions
TABLE:
Symbolic Microprogram
(Partial)
• Assume,
– MAP microinstruction at the end of
the FETCH routine caused a branch
to address ‘0’
– ADD routine is stored in address ‘0’
ADD Routine
• First microinstruction in the ADD
routine CALLS subroutine INDRCT,
conditioned on status bit ‘I’
– If I = 1, a branch to INDRCT occurs
– and RETURN address (address 1 in
this case) is stored in the subroutine
register SBR
– INDRCT subroutine has two
microinstructions:

– Memory has to be accessed (READ)

to get the Effective Address
• then transferred to AR (DRTAR)
– Return from subroutine (RET)
transfers the address from SBR to
CAR
• Thus returning to the Second
microinstruction of the ADD routine
• ADD instruction execution is carried out by the
microinstructions at addresses 1 and 2

• First MICROINSTRUCTION
– READS the operand from memory into DR

• Second MICROINSTRUCTION
– performs an ADD MICROOPERATION with the content of DR and
AC and
– then JUMPS back to the beginning of the FETCH routine

(addresses 0)
(addresses 1)
(addresses 2)
• BRANCH instruction
– should cause a branch to the
effective address if AC < 0 (sign
is negative)

• BRANCH routine starts by

=0
checking the value of S (status =1
bit )
• If S=0, NO branch occurs and =1

– Next microinstruction causes a

JUMP back to the FETCH
routine, WITHOUT altering the
content of PC
• If S = 1,
– First JMP microinstruction
transfers control to location
OVER
– Microinstruction at this
location calls the INDRCT
subroutine If I = 1
– Effective Address is then
transferred from AR to PC and
– microprogram JUMPS back to
the FETCH routine
• STORE routine
– again uses the INDRCT
subroutine if I=1
– content of AC is
transferred into DR
– Memory WRITE
operation is initiated to
store the content of DR
in a location specified by
the effective address in =1
AR

• EXCHANGE routine
– READS the operand from
the Effective Address
and places it in DR
– contents of DR and AC
are interchanged in the
third microinstruction
– original content of AC
that is now in DR is
stored back in memory
 Design of Control Unit
Figure shows the Decoding of
Microoperation fields with three
Decoders and some other connections

• For example,
• when F1 = 101 (DR to AR),
– there is a transfer from the
content of DR(0-10) to AR
• when F1 = 110 (PC to AR),
– there is a transfer from PC
to AR
• Outputs 5 and 6 of
Decoder F1 are connected
to the Load input of AR
• If AR is enabled,
– information from the
MULTIPLEXERS is
transferred to AR
• MUXs select
– information from DR when
output 5 is active
– from PC when output 5 is
inactive

Fig: Decoding of Microoperation fields

Microprogram Sequencer

• ADDRESS SELECTION PART of Microprogrammed control

unit is called a Microprogram Sequencer

• Purpose of a microprogram sequencer is

– to PRESENT an ADDRESS to the control memory
– so that a microinstruction may be read and executed

• Internal structure of a typical microprogram sequencer for

control unit is illustrated in below Fig.

Figure: Microprogrammed control organization

Figure shows a block diagram of
SELECTING the NEXT
MICROINSTRUCTION ADDRESS
(For Reference..)

CONTROL ADDRESS REGISTER (CAR)

receives the address from FOUR
DIFFERENT PATHS

• INCREMENTER increments the

content of the Control Address
Register (CAR) by one

• BRANCHING is achieved by
specifying the branch address in
one of the fields of the
microinstruction
– Conditional branching depends
on specific status bit in order to
determine its condition

• EXTERNAL ADDRESS is
transferred into control memory
via a MAPPING Logic Circuit

• RETURN ADDRESS for a

subroutine is stored in a
Subroutine Register (SBR)

Figure: Selection of address for control memory

• There are two multiplexers in the
circuit

• MUX1 External
– selects an address from one of four (MAP)
sources
– routes it into a control address register L
I0 3 2 1 0
CAR Input Load
I1 S1 MUX1 SBR
logic
T S0
• MUX2
– tests the value of a selected status bit
Incrementer
– result of the test is applied to an input 1
MUX2 Test
logic circuit I
S
Z Select
Clock CAR
• Output from CAR provides the
address for the control memory

• Content of CAR is incremented and

applied to MUX1 inputs and to the Control memory
subroutine register SBR
Microops CD BR AD
... ...
• Other three inputs to MUX1 come
– from the address field of the present
microinstruction
– from the output of SBR
– from an external source that MAPS
the instruction Fig: Microprogram Sequencer for a control memory
• MUX2 selects one of the status
bits from CD (condition) field
of microinstruction
External
(MAP)
• If the bit selected is equal to 1,
– the T (test) = 1; I0
L
3 2 1 0
– otherwise, T=0 Input Load
I1 S1 MUX1 SBR
logic
T S0

• T value together with the BR

(branch) field go to an input 1 Incrementer
logic circuit I
S MUX2 Test
Z Select
Clock CAR
• Input logic determine the type
of operations

• Typical sequencer operations Control memory

are:
Microops CD BR AD
– Increment
... ...
– branch or jump
– Call and return from
subroutine
– load an external address
– push or pop the stack
Fig: Microprogram Sequencer for a control memory
• The truth table for the input logic circuit is shown in below Table

• The truth table can be used to obtain the simplified Boolean

functions for the Input Logic Circuit:

S1 = I1
S0 = I1 I0 + I1’ T
L = I1 ’ I 0 T

TABLE: Input logic truth table for Microprogram Sequencer

BR Field Input MUX 1 Load SBR
I1 I0 T S1 S0 L