DS90C031B

www.ti.com SNLS051B – MARCH 1999 – REVISED MARCH 2013

DS90C031B LVDS Quad CMOS Differential Line Driver

Check for Samples: DS90C031B

1FEATURES DESCRIPTION
•
2 >155.5 Mbps (77.7 MHz) switching rates The DS90C031B is a quad CMOS differential line
driver designed for applications requiring ultra low
• High impedance LVDS outputs with power-off power dissipation and high data rates. The device
• ±350 mV differential signaling supports data rates in excess of 155.5 Mbps (77.7
• Ultra low power dissipation MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
• 400 ps maximum differential skew (5V, 25°C)
• 3.5 ns maximum propagation delay The DS90C031B accepts TTL/CMOS input levels and
translates them to low voltage (350 mV) differential
• Industrial operating temperature range output signals. In addition the driver supports a TRI-
• Pin compatible with DS26C31, MB571 (PECL) STATE function that may be used to disable the
and 41LG (PECL) output stage, disabling the load current, and thus
• Conforms to ANSI/TIA/EIA-644 LVDS standard dropping the device to an ultra low idle power state of
11 mW typical.
• Offered in narrow body SOIC package
• Fail-safe logic for floating inputs In addition, the DS90C031B provides power-off high
impedance LVDS outputs. This feature assures
minimal loading effect on the LVDS bus lines when
VCC is not present.
The DS90C031B and companion line receiver
(DS90C032B) provide a new alternative to high
power pseudo-ECL devices for high speed point-to-
point interface applications.

Connection Diagram
Functional Diagram

Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G16)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Driver Truth Table

Enables Input Outputs
EN EN* DIN DOUT+ DOUT−
L H X Z Z
All other combinations of ENABLE L L H
inputs H H L

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

(1)
Absolute Maximum Ratings
Supply Voltage (VCC) −0.3V to +6V
Input Voltage (DIN) −0.3V to (VCC + 0.3V)
Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V)
Output Voltage (DOUT+, DOUT−) −0.3V to +5.8V
Short Circuit Duration (DOUT+, DOUT−) Continuous
Maximum Package Power Dissipation at +25°C 1068 mW
Derate Power Dissipation 8.5 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range, Soldering (4 seconds) +260°C
Maximum Junction Temperature +150°C
ESD Rating
HBM, 1.5 kΩ, 100 pF ≥ 2kV
EIAJ, 0 Ω, 200 pF ≥ 250V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device
operation.

Recommended Operating Conditions

Min Typ Max Units
Supply Voltage (VCC) +4.5 +5.0 +5.5 V
Operating Free Air Temperature (TA) −40 +25 +85 °C

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Electrical Characteristics
(1) (2)
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol Parameter Test Conditions Pin Min Typ Max Units
VOD1 Differential Output Voltage RL = 100Ω (Figure 2) DOUT−, 250 345 450 mV
DOUT+
ΔVOD1 Change in Magnitude of VOD1 for 4 35 |mV|
Complementary Output States
VOS Offset Voltage 1.10 1.25 1.35 V
ΔVOS Change in Magnitude of VOS for 5 25 |mV|
Complementary Output States
VOH Output Voltage High RL = 100Ω 1.41 1.60 V
VOL Output Voltage Low 0.90 1.07 V
VIH Input Voltage High DIN, 2.0 VCC V
EN,
VIL Input Voltage Low GND 0.8 V
EN*
II Input Current VIN = VCC, GND, 2.5V or 0.4V −10 ±1 +10 μA
VCL Input Clamp Voltage ICL = −18 mA −1.5 −0.8 V
IOS Output Short Circuit Current VOUT = 0V (3) DOUT−, −3.5 −5.0 mA
DOUT+
IOZ Output TRI-STATE Current EN = 0.8V and EN* = 2.0V, −10 ±1 +10 μA
VOUT = 0V or VCC
IOFF Power - Off Leakage VO = 0V or 2.4V, VCC = 0V or Open −10 ±1 +10 μA
ICC No Load Supply Current Drivers DIN = VCC or GND VCC 1.7 3.0 mA
Enabled
DIN = 2.5V or 0.4V 4.0 6.5 mA
ICCL Loaded Supply Current Drivers RL = 100Ω (all channels), 15.4 21.0 mA
Enabled VIN = VCC or GND (all inputs)
ICCZ No Load Supply Current Drivers DIN = VCC or GND, 2.2 4.0 mA
Disabled EN = GND, EN* = VCC

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1.
(2) All typicals are given for: VCC = +5.0V, TA = +25°C.
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

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Switching Characteristics
(1) (2) (3)
VCC = +5.0V, TA = +25°C
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 5 pF 1.0 2.0 3.0 ns
(Figure 3 and Figure 4)
tPLHD Differential Propagation Delay Low to High 1.0 2.1 3.0 ns
tSKD Differential Skew |tPHLD – tPLHD| 0 80 400 ps
(4)
tSK1 Channel-to-Channel Skew 0 300 600 ps
tTLH Rise Time 0.35 1.5 ns
tTHL Fall Time 0.35 1.5 ns
tPHZ Disable Time High to Z RL = 100Ω, CL = 5 pF 2.5 10 ns
(Figure 5 and Figure 6)
tPLZ Disable Time Low to Z 2.5 10 ns
tPZH Enable Time Z to High 2.5 10 ns
tPZL Enable Time Z to Low 2.5 10 ns

(1) All typicals are given for: VCC = +5.0V, TA = +25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns.
(3) CL includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.

Switching Characteristics
(1) (2) (3)
VCC = +5.0V ± 10%, TA = −40°C to +85°C
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 5 pF 0.5 2.0 3.5 ns
(Figure 3 and Figure 4)
tPLHD Differential Propagation Delay Low to High 0.5 2.1 3.5 ns
tSKD Differential Skew |tPHLD – tPLHD| 0 80 900 ps
(4)
tSK1 Channel-to-Channel Skew 0 0.3 1.0 ns
(5)
tSK2 Chip to Chip Skew 3.0 ns
tTLH Rise Time 0.35 2.0 ns
tTHL Fall Time 0.35 2.0 ns
tPHZ Disable Time High to Z RL = 100Ω, CL = 5 pF 2.5 15 ns
(Figure 5 and Figure 6)
tPLZ Disable Time Low to Z 2.5 15 ns
tPZH Enable Time Z to High 2.5 15 ns
tPZL Enable Time Z to Low 2.5 15 ns

(1) All typicals are given for: VCC = +5.0V, TA = +25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns.
(3) CL includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.

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PARAMETER MEASUREMENT INFORMATION

Figure 2. Driver VOD and VOS Test Circuit

Figure 3. Driver Propagation Delay and Transition Time Test Circuit

Figure 4. Driver Propagation Delay and Transition Time Waveforms

Figure 5. Driver TRI-STATE Delay Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

Figure 6. Driver TRI-STATE Delay Waveform

Typical Application

Figure 7. Point-to-Point Application

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APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 7. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C031B differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The typical
output current is a mere 3.4 mA with a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode
requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete
the loop as shown in Figure 7. AC or unterminated configurations are not allowed. The 3.4 mA loop current will
develop a differential voltage of 340 mV across the 100Ω termination resistor which the receiver detects with a
240 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold
(340 mV – 100 mV = 240 mV). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground
as shown in Figure 8. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 680 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The fail-safe circuitry guarantees that the outputs are enabled and at a logic "0" (the true output is low and the
complement output is high) when the inputs are floating.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
The footprint of the DS90C031B is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver.
The DS90C031B is electrically similar to the DS90C031, but differs by supporting high impedance LVDS outputs
under power-off condition. This allows for multiple or redundant drivers to be used in certain applications. The
DS90C031B is offered in a space saving narrow SOIC (150 mil.) package.
For additional LVDS application information, see TI's LVDS Owner's Manual available through TI's website
http://www.ti.com/lsds/ti/analog/interface.page.

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Figure 8. Driver Output Levels

Pin Descriptions
Pin No. Name Description
1, 7, 9, 15 DIN Driver input pin, TTL/CMOS compatible
2, 6, 10, 14 DOUT+ Non-inverting driver output pin, LVDS levels
3, 5, 11, 13 DOUT− Inverting driver output pin, LVDS levels
4 EN Active high enable pin, OR-ed with EN*
12 EN* Active low enable pin, OR-ed with EN
16 VCC Power supply pin, +5V ± 10%
8 GND Ground pin

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TYPICAL PERFORMANCE CHARACTERISTICS

Power Supply Current Power Supply Current
vs Power Supply Voltage vs Temperature

Figure 9. Figure 10.

Power Supply Current Power Supply Current

vs Power Supply Voltage vs Temperature

Figure 11. Figure 12.

Output TRI-STATE Current Output Short Circuit Current

vs Power Supply Voltage vs Power Supply Voltage
±3
IOS ± Output Short Circuit Current (mA)

TA = 25 °C
VIN = 0V or 5V
±3.2
VOUT = 0V

±3.4

±3.6

±3.8

±4
4.5 4.75 5 5.25 5.5
VCC ± Power Supply Voltage (V)
Figure 13. Figure 14.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Differential Output Voltage Differential Output Voltage
vs Power Supply Voltage vs Ambient Temperature

Figure 15. Figure 16.

Output Voltage High vs Output Voltage High vs

Power Supply Voltage Ambient Temperature

Figure 17. Figure 18.

Output Voltage Low vs Output Voltage Low vs

Power Supply Voltage Ambient Temperature

Figure 19. Figure 20.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Offset Voltage vs Offset Voltage vs
Power Supply Voltage Ambient Temperature

Figure 21. Figure 22.

Power Supply Current Power Supply Current

vs Frequency vs Frequency

Figure 23. Figure 24.

Differential Output Voltage Differential Propagation Delay

vs Load Resistor vs Power Supply Voltage

Figure 25. Figure 26.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Differential Propagation Delay Differential Skew vs
vs Ambient Temperature Power Supply Voltage

Figure 27. Figure 28.

Differential Skew vs Differential Transition Time

Ambient Temperature vs Power Supply Voltage

Figure 29. Figure 30.

Differential Transition Time

vs Ambient Temperature

Figure 31.

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REVISION HISTORY

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

DS90C031BTM ACTIVE SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90C031BTM

DS90C031BTM/NOPB ACTIVE SOIC D 16 48 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 DS90C031BTM

& no Sb/Br)
DS90C031BTMX ACTIVE SOIC D 16 TBD Call TI Call TI -40 to 85 DS90C031BTM

DS90C031BTMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 DS90C031BTM

& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C031BTMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90C031BTMX/NOPB SOIC D 16 2500 367.0 367.0 35.0

Pack Materials-Page 2
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