DS90LV017A

www.ti.com SNLS022C – MARCH 2000 – REVISED APRIL 2013

DS90LV017A LVDS Single High Speed Differential Driver

Check for Samples: DS90LV017A

1FEATURES DESCRIPTION
•
2 >600 Mbps (300 MHz) Switching Rates The DS90LV017A is a single LVDS driver device
optimized for high data rate and low power
• 0.3 ns Typical Differential Skew applications. The DS90LV017A is a current mode
• 0.7 ns Maximum Differential Skew driver allowing power dissipation to remain low even
• 1.5 ns Maximum Propagation Delay at high frequency. In addition, the short circuit fault
current is also minimized. The device is designed to
• 3.3V Power Supply Design
support data rates in excess of 600Mbps (300MHz)
• ±355 mV Differential Signaling utilizing Low Voltage Differential Signaling (LVDS)
• Low Power Dissipation (23 mW @ 3.3V Static) technology.
• Flow-Through Design Simplifies PCB Layout The device is in a 8-lead SOIC package. The
• Interoperable with Existing 5V LVDS Devices DS90LV017A has a flow-through design for easy
PCB layout. The differential driver outputs provides
• Power Off Protection (Outputs in High
low EMI with its typical low output swing of 355 mV.
Impedance) The DS90LV017A can be paired with its companion
• Conforms to TIA/EIA-644 Standard single line receiver, the DS90LV018A, or with any of
• 8-Lead SOIC Package Saves Space TI's LVDS receivers, to provide a high-speed point-to-
point LVDS interface.
• Industrial Temperature Operating Range
– (−40°C to +85°C)

Connection Diagram

Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G8)

Functional Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90LV017A
SNLS022C – MARCH 2000 – REVISED APRIL 2013 www.ti.com

Absolute Maximum Ratings (1)

Supply Voltage (VCC) −0.3V to +4V
Input Voltage (DI) −0.3V to +3.6V
Output Voltage (DO±) −0.3V to +3.9V
D Package 1190 mW
Maximum Package Power Dissipation @ +25°C
Derate D Package 9.5 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering (4 sec.) +260°C
(HBM 1.5 kΩ, 100 pF) ≥ 8kV
(EIAJ 0 Ω, 200 pF) ≥ 1000V
ESD Ratings
(CDM) ≥ 1000V
(IEC direct 330 Ω, 150 pF) ≥ 4kV

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.

Recommended Operating Conditions

Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Temperature (TA) −40 25 +85 °C

Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2) (3)
Symbol Parameter Conditions Pin Min Typ Max Units
DIFFERENTIAL DRIVER CHARACTERISTICS
VOD Output Differential Voltage RL = 100Ω DO+, 250 355 450 mV
(Figure 2) DO−
ΔVOD VOD Magnitude Change 1 35 mV
VOH Output High Voltage 1.4 1.6 V
VOL Output Low Voltage 0.9 1.1 V
VOS Offset Voltage 1.125 1.2 1.375 V
ΔVOS Offset Magnitude Change 0 3 25 mV
IOXD Power-off Leakage VOUT = VCC or GND, VCC = 0V ±1 ±10 μA
IOSD Output Short Circuit Current −5.7 −8 mA
VIH Input High Voltage DI 2.0 VCC V
VIL Input Low Voltage GND 0.8 V
IIH Input High Current VIN = 3.3V or 2.4V ±2 ±10 μA
IIL Input Low Current VIN = GND or 0.5V ±1 ±10 μA
VCL Input Clamp Voltage ICL = −18 mA −1.5 −0.6 V
ICC Power Supply Current No Load VIN = VCC or GND VCC 5 8 mA
RL = 100Ω 7 10 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD.
(2) All typicals are given for: VCC = +3.3V and TA = +25°C.
(3) The DS90LV017A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.

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Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified (1) (2) (3) (4)
Symbol Parameter Conditions Min Typ Max Units
DIFFERENTIAL DRIVER CHARACTERISTICS
tPHLD Differential Propagation Delay High to Low RL = 100Ω, CL = 15 pF 0.3 0.8 1.5 ns
tPLHD Differential Propagation Delay Low to High (Figure 3 and Figure 4) 0.3 1.1 1.5 ns
tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (5) 0 0.3 0.7 ns
(6)
tSKD3 Differential Part to Part Skew 0 1.0 ns
tSKD4 Differential Part to Part Skew (7) 0 1.2 ns
tTLH Transition Low to High Time 0.2 0.5 1.0 ns
tTHL Transition High to Low Time 0.2 0.5 1.0 ns
fMAX Maximum Operating Frequency (8) 350 MHz

(1) All typicals are given for: VCC = +3.3V and TA = +25°C.
(2) These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(3) CL includes probe and fixture capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
(5) tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
(8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD >
250mV.

Parameter Measurement Information

Figure 2. Differential Driver DC Test Circuit

Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit

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Parameter Measurement Information (continued)

Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms

APPLICATION INFORMATION

Table 1. Device Pin Descriptions

Pin # Name Description
2 DI1 TTL/CMOS driver input pins
7 DO1+ Non-inverting driver output pin
8 DO1− Inverting driver output pin
4 GND Ground pin
1 VCC Positive power supply pin, +3.3V ± 0.3V
3, 5, 6 NC No connect

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Typical Performance Curves

Output High Voltage vs Output Low Voltage vs
Power Supply Voltage Power Supply Voltage

Figure 5. Figure 6.

Output Short Circuit Current vs Differential Output Voltage

Power Supply Voltage vs Power Supply Voltage

Figure 7. Figure 8.

Differential Output Voltage Offset Voltage vs

vs Load Resistor Power Supply Voltage

Figure 9. Figure 10.

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Typical Performance Curves (continued)

Power Supply Current Power Supply Current vs
vs Frequency Power Supply Voltage

Figure 11. Figure 12.

Power Supply Current vs Differential Propagation Delay vs

Ambient Temperature Power Supply Voltage

Figure 13. Figure 14.

Differential Propagation Delay vs Differential Skew vs

Ambient Temperature Power Supply Voltage

Figure 15. Figure 16.

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Typical Performance Curves (continued)

Differential Skew vs Transition Time vs
Ambient Temperature Power Supply Voltage

Figure 17. Figure 18.

Transition Time vs
Ambient Temperature

Figure 19.

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DS90LV017A
SNLS022C – MARCH 2000 – REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 7

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 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DS90LV017ATM NRND SOIC D 8 95 Non-RoHS Call TI Level-1-235C-UNLIM -40 to 85 LV17A

& Green TM
DS90LV017ATM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV17A
TM
DS90LV017ATMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV17A
TM

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90LV017ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV017ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DS90LV017ATM D SOIC 8 95 495 8 4064 3.05
DS90LV017ATM D SOIC 8 95 495 8 4064 3.05
DS90LV017ATM/NOPB D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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