SN65LVDS94

www.ti.com SLLS298F – MAY 1998 – REVISED JANUARY 2006

LVDS SERDES RECEIVER

FEATURES DGG PACKAGE
• 4:28 Data Channel Expansion at up to 1.904 (TOP VIEW)
Gigabits per Second Throughput
• Suited for Point-to-Point Subsystem D22 1 56 VCC
Communication With Very Low EMI D23 2 55 D21
• 4 Data Channels and Clock Low-Voltage D24 3 54 D20
Differential Channels in and 28 Data and GND 4 53 D19
Clock Out Low-Voltage TTL Channels Out D25 5 52 GND
D26 6 51 D18
• Operates From a Single 3.3-V Supply and
D27 7 50 D17
250 mW (Typ)
LVDSGND 8 49 D16
• 5-V Tolerant SHTDN Input
A0M 9 48 VCC
• Rising Clock Edge Triggered Outputs A0P 10 47 D15
• Bus Pins Tolerate 4-kV HBM ESD A1M 11 46 D14
• Packaged in Thin Shrink Small-Outline A1P 12 45 D13
Package With 20 Mil Terminal Pitch LVDSVCC 13 44 GND
• Consumes <1 mW When Disabled LVDSGND 14 43 D12
A2M 15 42 D11
• Wide Phase-Lock Input Frequency Range
A2P 16 41 D10
20 MHz to 68 MHz
CLKINM 17 40 VCC
• No External Components Required for PLL
CLKINP 18 39 D9
• Meets or Exceeds the Requirements of ANSI A3M 19 38 D8
EIA/TIA-644 Standard A3P 20 37 D7
• Industrial Temperature Qualified LVDSGND 21 36 GND
TA = -40°C to 85°C PLLGND 22 35 D6
• Replacement for the DS90CR286 PLLVCC 23 34 D5
PLLGND 24 33 D4
SHTDN 25 32 D3
CLKOUT 26 31 VCC
D0 27 30 D2
GND 28 29 D1

DESCRIPTION
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift
registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended
LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the
expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1998–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS94
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SLLS298F – MAY 1998 – REVISED JANUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)
The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low
level on this signal clears all internal registers to a low level.
The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.

FUNCTIONAL BLOCK DIAGRAM

Serial-In/Parallel-Out
Shift Register
A0P D0
Serial In A,B, ...G
A0M D1
CLK D2
D3
D4
D6
D7
Serial-In/Parallel-Out
Shift Register
A1P
Serial In A,B, ...G D8
A1M D9
CLK D12
D13
D14
D15
D18
Serial-In/Parallel-Out
Shift Register
A2P
Serial In A,B, ...G D19
A2M D20
CLK D21
D22
D24
D25
D26
Serial-In/Parallel-Out
Shift Register
A3P
Serial In A,B, ...G D27
A3M D5
CLK D10
D11
D16
D17
Control Logic
D23
SHTDN

7× Clock/PLL
CLK
CLKINP
Clock In Clock Out CLKOUT
CLKINM

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CLKIN

Previous Cycle Current Cycle Next Cycle

A0 D7 D6 D4 D3 D2 D1 D0 D7+1

D0-1

A1 D18 D15 D14 D13 D12 D9 D8 D18+1

D86-1

A2 D26 D25 D24 D22 D21 D20 D19 D26+1

D19-1

A3 D23 D17 D16 D11 D10 D5 D27 D23+1

D27-1

CLKOUT

Dn Dn-1 Dn Dn+1

Figure 1. SN65LVDS94 Load and Shift Sequences

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

VCC VCC VCC

300 kΩ 300 kΩ

50 Ω 50 Ω
D Output
AnP AnM SHTDN

7V 7V
7V 7V
300 kΩ

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SN65LVDS94
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SLLS298F – MAY 1998 – REVISED JANUARY 2006

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature (unless otherwise noted)
UNIT
VCC (2) Supply voltage range -0.3 V to 4 V
Voltage range at any terminal (except SHTDN) -0.5 V to VCC + 0.5 V
Voltage range at SHTDN terminal -0.5 V to VCC + 3 V
Bus pins (Class 3A) 4 KV
Bus pins (Class 2B) 200 V
Electrostatic discharge (3)
All pins (Class 3A) 3 KV
All pins (Class 2B) 200 V
Continuous total power dissipation (see Dissipation Rating Table)
TA Operating free-air temperature range -40°C to 85°C
Tstg Storage temperature range -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 260°C
seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals unless otherwise noted.
(3) This rating is measured using MIL-STD-883C Method, 3015.7.

DISSIPATION RATING TABLE

TA≤ 25°C DERATING FACTOR (1) TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
DGG 1377 mW 11 mW/°C 882 mW 717 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6
VIH High-level input voltage (SHTDN) 2
VIL Low-level input voltage (SHTDN) 0.8
|VID| Magnitude of differential input voltage 0.1 0.6
V

VIC, see
V
V 
Figure 2 and Common-mode input voltage ID 2.4
ID
Figure 3 2 2
VCC-0.8
TA Operating free-air temperature -40 85 °C

TIMING REQUIREMENTS
MIN NOM MAX UNIT
tc (1) Input clock period 14.7 tc 50 ns

(1) tc is defined as the mean duration of a minimum of 32,000 clock periods.

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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIT+ Positive-going differential input voltage threshold 100
Negative-going differential input voltage mV
VIT- -100
threshold (2)
VOH High-level output voltage IOH = -4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
Disabled, all inputs open 280 µA
Enabled, AnP at 1 V and AnM at 1.4
V, 62 84 mA
ICC Quiescent current (average) tc = 15.38 ns
Enabled, CL = 8 pF (5 places),
Worst-case pattern, see Figure 4, 107 mA
tc = 15.38 ns
IIH High-level input current (SHTDN) VIH = VCC ±20 µA
IIL Low-level input current (SHTDN) VIL = 0 V ±20 µA
IIN Input current (A and CLKIN inputs) 0 V ≤ VI≤ 2.4 V ±20 µA
IOZ High-impedance output current VO = 0 V or VCC ±10 µA

(1) All typical values are VCC = 3.3 V, TA = 25°C.

(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going input voltage threshold only.

SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Data setup time, D0 through D27 to
tsu 4 6
CLKOUT
CL = 8 pF See Figure 5 ns
Data hold time, CLKOUT to D0 through
th 4 6
D27
Receiver input skew margin (1), see tc = 15.38 ns (±0.2%), TA = 0°C to 85°C 490 800
tRSKM ps
Figure 6 |Input clock jitter| <50 ps (2) TA = -40°C to 0°C 390
Delay time, input clock to output clock, see
td tc = 15.38 ns (±0.2%) 3.7 ns
Figure 6
tc = 15.38 + 0.75 sin (2π500E3t)±0.05 ns,
±80
Change in output clock period from cycle to See Figure 7
∆tC(O) ps
cycle (3) tc = 15.38 + 0.75 sin (2≠3E6t) ±0.05 ns,
±300
See Figure 7
ten Enable time, SHTDN to phase lock See Figure 8 1 ms
tdis Disable time, SHTDN to Off state See Figure 9 400 ns
tt Output transition time (tr or tf) CL = 8 pF 3 ns
tw Output clock pulse duration 0.43 tc ns

tc
–ts
h.
(1) tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. It is defined by 14
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) ∆tC(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.

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PARAMETER MEASUREMENT INFORMATION

AP

VID
AM

(VIAP + VIAM)/2 VIAP

VIC
VIAM

Figure 2. Voltage Definitions

COMMON-MODE INPUT VOLTAGE

vs
DIFFERENTIAL INPUT VOLTAGE AND VCC
2.5
MAX at >3.15 V
VIC – Common-Mode Input Voltage – V

MAX at 3 V
2

1.5

0.5
MIN

0
0 0.1 0.2 0.3 0.4 0.5 0.6
|VID|– Differential Input Voltage and VCC – V

Figure 3. Recommended VIC Versus VID and VCC

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SLLS298F – MAY 1998 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

CLKIN/
CLKOUT

EVEN Dn

ODD Dn

Figure 4. Worst-Case Power Test Pattern

tsu
VOH
70%
D0–27
30%
VOL
th
VOH
70%
CLKOUT

30%
VOL

Figure 5. Setup and Hold Time Measurements

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SN65LVDS94
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SLLS298F – MAY 1998 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Tektronix An DUT D0−D27

HFS9003/HFS9DG1 Tektronix Microwave
Stimulus System Logic Multi-BERT-100RX
(Repeating Patterns CLKIN CLKOUT Word Error Detector
1110111 and 0001000)

CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs.
The magnitude of the advance or delay is tRSKM.

tc
4/7 tc ± tRSKM
ts
3/7 tc ± tRSKM
th

AnP

and AnM

CLKIN

7×CLK
(Internal)
td

CLKOUT

tr < 1 ns

≅ 300 mV
90%
CLKIN or An
0V
10%
≅ −300 mV

VOH

CLKOUT 1.4 V

VOL

Figure 6. Receiver Input Skew Margin and td Definitions

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SLLS298F – MAY 1998 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Device
+
Reference Σ VCO Under
Test
+
Modulation
v(t) = A sin(2πfmodt)

HP8656B Signal HP8665A Synthesized Device Under DTS2070C

Generator, Signal Generator, Test Digital Time
0.1 MHz–990 MHz 0.1 MHz–4200 MHz Scope

RF Output Modulation Input Output CLKIN CLKOUT Input

Figure 7. Output Clock Jitter Test Setup

CLKIN

An

ten

SHTDN

Dn Invalid Valid

Figure 8. Enable Time Waveforms

CLKIN

tdis

SHTDN

CLKOUT

Figure 9. Disable Time Waveforms

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SN65LVDS94
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SLLS298F – MAY 1998 – REVISED JANUARY 2006

TYPICAL CHARACTERISTICS
WORST-CASE SUPPLY CURRENT
vs
FREQUENCY
140

120

I CC − Supply Current − mA
100
VCC = 3.6 V
80
VCC = 3 V VCC = 3.3 V

60

40

20

0
30 40 50 60 70
f − Frequency − MHz
Figure 10.

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SLLS298F – MAY 1998 – REVISED JANUARY 2006

APPLICATION INFORMATION

16-BIT BUS EXTENSION

In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the
backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus
is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The
data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is
also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the
receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then
demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and
then all are presented to the parallel output port of the receiver.
LVDS
16-Bit Interface 16-Bit
BTL Bus TTL 0 To 10 Meters TTL BTL Bus
Interface Interface (Media Dependent) Interface Interface
SN75L0DS93 SN75LV0S94

D0–D7 8 8 D0–D7
SN74FB2032 SN74FB2032

D8–D15 8 8 D8–D15
SN74FB2032 SN74FB2032

CLK XMIT Clock RCV Clock CLK

Backplane Backplane
Bus Bus

Figure 11. 16-Bit Bus Extension

16-BIT BUS EXTENSION WITH PARITY

In the previous application we did not have a checking bit that would provide assurance that the data crosses the
link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 12. The
device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity generator
takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then
passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the
on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The
synchronized LVDS data/parity and clock arrive at the receiver.
The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the
parity calculations. These devices compare their corresponding input bytes with the value received on the parity
bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.

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APPLICATION INFORMATION (continued)

LVDS
16-Bit TTL Interface TTL 16-Bit
BTL Bus TTL Interface 0 To 10 Meters Interface TTL BTL Bus
Interface Interface W/Parity (Media Dependent) W/Parity Interface Interface
SN75LVDS93 SN75LVDS94

D0–D7 8 8 D0–D7
SN74FB2032 9 Bit Latchable 9 Bit Latchable SN74FB2032
Transceiver/ With Parity Parity Transceiver/ With
Parity Generator Parity Generator

D8–D15 8 8 D8–D15
SN74FB2032 9 Bit Latchable 9 Bit Latchable SN74FB2032
Transceiver/ With Parity Parity Transceiver/ With
Parity Generator Parity Generator

Parity
Error
CLK XMIT Clock RCV Clock CLK

Backplane Backplane
Bus Bus

Figure 12. 16-Bit Bus Extension With Parity

LOW COST VIRTUAL BACKPLANE TRANSCEIVER

Figure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a
VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem
serialized links.
Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the
devices shown in Figure 13, functions such as parity and delay lines for control signals could be included. Using
additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines
properly.
The designer may choose to implement an independent clock oscillator at each end of the link and then use a
PLL to synchronize LVDS serdes's parallel I/O to the backplane bus. Resynchronizing FIFOs may also be
required.

Bus LVDS Serdes LVDS Serdes Bus

Transceivers Transmitter Receiver Transceivers
TTL TTL
LVDS
Inputs Outputs
Backplane Serial Links Backplane
Up To Up To
Bus 4 or 5 Bus
21 or 28 21 or 28
Pairs
Bits Bits
Bus LVDS Serdes LVDS Serdes Bus
Transceivers Transmitter Receiver Transceivers

Figure 13. Virtual Backplane Transceiver

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 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SN65LVDS94DGG ACTIVE TSSOP DGG 56 35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65LVDS94DGGG4 ACTIVE TSSOP DGG 56 35 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65LVDS94DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65LVDS94DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS94DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS94DGGR TSSOP DGG 56 2000 367.0 367.0 45.0

Pack Materials-Page 2
 MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27
0,50 0,08 M
0,17
48 25

6,20 8,30
6,00 7,90 0,15 NOM

Gage Plane

0,25
1 24
0°– 8°
A 0,75
0,50

Seating Plane
0,15
1,20 MAX 0,10
0,05

PINS **
48 56 64
DIM

A MAX 12,60 14,10 17,10

A MIN 12,40 13,90 16,90

4040078 / F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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