Characterisc Analysis of NMOS and PMOS

EE 519P / VL 403: CMOS Digital IC Design Practicum

Aman Mohammad(T25130), S Sundra Murthy(T25124), Shubham Meena(B23467)

School of Computing and Electrical Engineering
Indian Institute of Technology Mandi
Himachal Pradesh, India

Abstract—This experiment explores the intrinsic behavior of III. NMOS C HARACTERIZATION

NMOS and PMOS transistors through Cadence-based simula-
tions, bridging theory with practical device analysis. By con- A. Theoretical Background
structing testbenches and performing DC sweeps, the drain An NMOS transistor is a majority carrier device in which
current dependence on VGS , VDS , and body bias VSB was system- electrons form the inversion channel. Conduction begins when
atically studied. Key device parameters such as threshold voltage
VT and saturation voltage VDsat were extracted, revealing their
the gate to source voltage (VGS ) exceeds the threshold voltage
variation with bulk bias. The results validate fundamental MOS- (VT ), creating a conductive channel between the drain and
FET principles while highlighting the critical role of body effect source. The device operation can be divided into three regions:
in CMOS design, providing a strong foundation for advanced • Cut-off / Subthreshold Region: For VGS < VT , no
VLSI applications.
Index Terms—NMOS, PMOS, Cadence Virtuoso, Body Effect,
strong inversion channel is formed. The drain current ID
Threshold Voltage, Saturation Voltage, DC Characterization is very small and dominated by diffusion of minority car-
riers. In modern short-channel devices, this subthreshold
I. I NTRODUCTION current follows an exponential relation:
!
The MOSFET is the fundamental device in modern VLSI VGS − VT
ID ∝ exp ,
circuits. Precise understanding of its current–voltage behavior nVth
is essential for circuit design, modeling, and performance
prediction. In this work, we carry out transistor-level char- where Vth is the thermal voltage and n is the subthreshold
acterization of NMOS and PMOS devices in a 1.8 V CMOS slope factor. This region is important in low-power design
process using Cadence Virtuoso. Both devices were analyzed due to leakage currents.
under basic DC biasing and body bias conditions to extract • Linear / Triode Region: When VGS > VT and VDS <
key electrical parameters. VGS −VT , a conductive channel exists and the device be-
The paper is structured as follows. Section II describes the haves like a voltage-controlled resistor. The drain current
design methodology; Sections III and IV discuss NMOS and is approximately:
PMOS characteristics, respectively; Section V addresses body- 2
 
W VDS
effect analysis and parameter extraction; Section VI concludes ID ≈ µn Cox (VGS − VT )VDS − ,
L 2
the work.
where µn is electron mobility, Cox is oxide capacitance
II. D ESIGN M ETHODOLOGY per unit area, and W/L is the transistor aspect ratio. ID
increases nearly linearly with VDS in this region.
All simulations were performed in the Cadence Virtuoso
• Saturation Region: For VDS ≥ VGS − VT , the channel
Analog Design Environment (ADE). The following method-
near the drain pinches off, and the drain current becomes
ology was used:
almost independent of VDS . In the long-channel model:
• The size of the transistor was chosen as W = 10 µm,
W
L = 180 nm to give clarity to the results. ID ≈ 12 µn Cox (VGS − VT )2 .
• Separate schematics were created for NMOS and PMOS
L
devices with independent DC sources for gate, drain, In real devices, channel-length modulation causes ID to
source, and bulk terminals. increase slightly with VDS , modeled by a factor (1 +
• DC analyzes were configured to sweep the gate and drain λVDS ) where λ is the CLM parameter.
voltages from 0 V to 1.8 V. In addition to these regions, two key effects further influence
• Body-bias sweeps were performed by varying VSB be- NMOS behavior:
tween 0 V and 1.8 V. • Body Effect: The threshold voltage is not constant but
• The extraction of VT and VDSAT was performed using depends on the source-to-bulk voltage VSB :
ADE marker tools, based on constant current and knee p p 
voltage methods. VT (VSB ) = VT 0 + γ 2ϕF + VSB − 2ϕF ,
 where VT 0 is the zero-bias threshold, γ is the body-effect 10-4
I D vs VDS for different V GS
2.5
coefficient, and ϕF is the Fermi potential. This effect
VGS=0
makes the device less conductive as VSB increases. VGS=0.45
2 VGS=0.9
• Velocity Saturation: At high electric fields, carrier ve- VGS=1.35
VGS=1.8
locity saturates at vsat , limiting ID growth and causing
1.5
a departure from the ideal quadratic dependence on VGS .

I D (A)
This is prominent in short-channel devices.
1
Thus, NMOS characteristics span weak inversion, strong inver-
sion, and velocity saturation, all of which must be accounted
0.5
for in practical design and modeling.
B. NMOS Schematic 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
V DS (V)

Fig. 3: NMOS ID –VDS for multiple VGS values at VSB = 0.

Vgs −Vbs Vds NMOS behavior, but with reversed voltage polarities and lower
+ + + mobility due to holes. The main regions of operation are:
− − • Cut-off / Subthreshold Region: For VSG < |VT p |, no
inversion channel is present and the drain current ID is
nearly zero, apart from subthreshold leakage. Similar to
NMOS, the leakage current increases exponentially with
VSG : !
VSG − |VT p |
Fig. 1: NMOS schematic |ID | ∝ exp ,
nVth

C. Results and Discussion where Vth is the thermal voltage. This region dominates
standby power consumption.
I D vs VGS for different V DS
• Linear / Triode Region: When VSG > |VT p | and VSD <
10-5
7
VDS=0
VSG − |VT p |, the device behaves like a voltage-controlled
6
VDS=0.45
VDS=0.9
resistor. The current equation is:
VDS=1.35  2

VDS=1.8 W VSD
5 |ID | ≈ µp Cox (VSG − |VT p |)VSD − ,
L 2
4
where µp is hole mobility. Compared to NMOS, PMOS
I D (A)

3 devices generally drive less current for the same geometry

because µp < µn .
2
• Saturation Region: For VSD ≥ VSG −|VT p |, the channel
1 near the drain end pinches off and the current saturates.
The long-channel expression is:
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
W
V GS (V) (VSG − |VT p |)2 .
|ID | ≈ 21 µp Cox
L
Fig. 2: NMOS ID –VGS for multiple VDS values at VSB = 0.
As with NMOS, channel-length modulation slightly in-
creases ID with VSD , modeled by (1 + λVSD ).
Fig. 2 shows that ID rises quadratically with (VGS − VT )
Two important secondary effects also govern PMOS operation:
in saturation, while in the linear region it scales with VDS .
• Body Effect: The threshold voltage magnitude increases
From Fig. 3, VDSAT is identified at the knee where current
saturates. Channel-length modulation is evident from the finite with source-to-bulk bias VSB , given by
p 
slope in saturation. |VT p (VSB )| = |VT p0 | + γp 2ϕF + VSB − 2ϕF ,
p

IV. PMOS C HARACTERIZATION

where |VT p0 | is the zero-bias threshold, γp is the body-
A. Theoretical Background effect coefficient, and ϕF is the Fermi potential. This
A PMOS transistor is a majority carrier device where effect makes it harder for the device to turn on as VSB
holes form the inversion channel. Conduction begins when increases.
the source-to-gate voltage (VSG ) exceeds the magnitude of • Velocity Saturation: At high vertical fields, hole velocity
the threshold voltage (|VT p |). The device operation mirrors saturates, reducing the ideal quadratic dependence of
 ID on (VSG − |VT |). This effect is stronger in short- In Fig. 6, VDSAT is extracted at the transition from linear
channel PMOS devices, further lowering their effective to saturation region, with channel-length modulation present
drive strength. in saturation.
Thus, PMOS devices exhibit the same fundamental regions
of operation as NMOS, but with reduced current capability V. B ODY E FFECT AND PARAMETER E XTRACTION
due to lower hole mobility and slightly different body-effect A. Body Bias Dependence
behavior. The threshold voltage is modified by source-to-body volt-
B. PMOS Schematic age:
p p

VT (VSB ) = VT 0 + γ 2ϕF + VSB − 2ϕF .
Vgs − Vsb + − This increases VT for NMOS and increases |VT | for PMOS.
+ +
− Vds 2.5
10-4
I D vs VGS for different V SB

VSB=0
VSB=0.45
VSB=0.9
2 VSB=1.35
VSB=1.8

Fig. 4: PMOS schematic 1.5

I D (A)
1
C. Results and Discussion
0.5
I D vs VGS for different V DS
10-5
1

0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
-1 VDS= 0 V GS (V)
VDS= -0.3
-2 VDS= -0.9
VDS= -1.2 Fig. 7: NMOS ID –VGS with varying VSB
-3 VDS= -1.8
I D (A)

-4

-5 I D vs VGS for different V SB

10-5
0
-6
-1
-7 VSB= 0
VSB= -0.3
-2 VSB= -0.9
-8
VSB= -1.2
-9 -3 VSB= -1.8
-1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0
V GS (V) -4
I D (A)

Fig. 5: PMOS ID –VGS for multiple VDS values at VSB = 0. -5

-6

Fig. 5 shows the expected quadratic dependence of current -7

on overdrive VGS − |VT |. -8

-9
I D vs VDS for different V GS -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0
10-5 V GS (V)
0

-0.5
Fig. 8: PMOS ID –VGS with varying VSB

-1 The body effect also influences the output characteristics.

-1.5
As VSB increases, the effective threshold voltage increases,
I D (A)

requiring higher gate overdrive to achieve the same drain

-2 current. This effect is visible in the ID –VDS characteristics
-2.5
shown in Figs. 9 and 10.
VGS= 0
VGS= -0.3
From Figs. 9 and 10, we observe that increasing VSB
-3 VGS= -0.9
VGS= -1.2
reduces the drain current for both NMOS and PMOS devices.
-3.5
VGS= -1.8 This reduction is due to the increased threshold voltage,
-1.8 -1.6 -1.4 -1.2 -1 -0.8
V DS (V)
-0.6 -0.4 -0.2 0
which decreases the effective gate overdrive (VGS − VT ) or
(VSG − |VT |). The saturation voltage VDSAT also shifts to
Fig. 6: PMOS ID –VDS for multiple VGS values at VSB = 0. higher values with increasing body bias.
 I D vs VDS for different V SB V T vs VSB for NMOS
10-4
2.5 0.7

2 0.65

VSB=0
VSB=0.45
1.5 VSB=0.9 0.6
VSB=1.35
I D (A)

V T(V)
VSB=1.8

1 0.55

0.5 0.5

0 0.45
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
V GS (V) V SB (V)

Fig. 9: NMOS ID –VDS with varying VSB Fig. 11: VT vs VSB (NMOS)

I D vs VDS for different V SB V T vs VSB for PMOS

10-5 -0.5
1
VSB= 0
0 VSB= -0.3 -0.55
VSB= -0.9
-1 VSB= -1.2
VSB= -1.8 -0.6
-2
-0.65
-3

V T(V)
I D (A)

-4 -0.7

-5 -0.75

-6
-0.8
-7
-0.85
-8

-9 -0.9
-1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2
V DS (V) V SB (V)

Fig. 10: PMOS ID –VDS with varying VSB Fig. 12: VT vs VSB (PMOS)

TABLE I: Extracted VT and VDSAT values (NMOS)

age increases with VSB for NMOS and becomes more negative
VSB (V) VT (V) VDSAT (V) for PMOS. The saturation voltage follows (VGS − VT ).
0.0 0.47 1.33
0.45 0.54 1.26 VI. C ONCLUSION
0.9 0.59 1.21
1.35 0.63 1.17 This experiment presented a complete DC characterization
1.8 0.66 1.14 of NMOS and PMOS devices in Cadence Virtuoso using
a 1.8 V CMOS process. Device operation was validated
TABLE II: Extracted VT and VDSAT values (PMOS) through ID –VGS and ID –VDS plots, while body-bias sweeps
confirmed theoretical predictions of threshold voltage shift.
VSB (V) VT (V) VDSAT (V)
Extracted VT and VDSAT parameters matched expected trends,
-0.0 -0.50 -1.30 demonstrating the accuracy of Virtuoso for device-level anal-
-0.3 -0.58 -1.22
-0.9 -0.72 -1.08
ysis.
-1.2 -0.77 -1.03
-1.8 -0.86 -0.94 VII. R EFERENCES
R EFERENCES
[1] MOSFET Operating Point for Simulation and Design - Cadence
B. Extracted Parameters Blog Available at: https://resources.pcb.cadence.com/blog/2025-mosfet-
operating-point-for-simulation-and-design
In this work, the threshold voltage is obtained directly from [2] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd
the transfer characteristics by identifying the point where the ed., Wiley-Interscience, 2006. [Chapters on MOSFETs and device
characteristics]
drain current begins to rise. A tangent is drawn at this region [3] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
of the curve, and its intersection with the voltage axis is taken 2001. [Focus on NMOS and PMOS behavior in analog circuits]
as VT . From body-sweep plots, VT and VDSAT were extracted.
Results are summarized below.
The extracted values confirm the body effect: threshold volt-