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DEPARTMENT OF ECE
IV B.Tech I Semester
VLSI DESIGN
 1
UNIT-I
DAY-1
Topics to be covered:
 Introduction to IC Technology
 Moore's Law
1. What is VLSI?
Very-large-scale integration (VLSI): It is the process of creating an integrated
circuit (IC) by combining thousands of transistors into a single chip. VLSI
began in 1970s when complex semiconductor and communication
technologies were being developed. The microprocessor is a VLSI device.
Before the introduction of VLSI technology most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into
one chip.
2. What are the four generations of Integration Circuits?
The invention of the transistor by William B. Shockley, Walter H. Brattain and
John Bardeen of Bell Telephone Laboratories was followed by the
development of the Integrated Circuit (IC). The very first IC emerged at the
beginning of 1960 and since that time there have already been four
generations of ICs:
 SSI (Small Scale Integration) Level of integrations No. of Gates
 MSI (Medium Scale Integration) SSI 10
 LSI (Large Scale Integration) MSI 1000
 VLSI (Very Large Scale LSI 10,000
Integration) VLSI > 10k

3.What are the advantages of IC?

 Size is less
 High Speed
 Less Power Dissipation
 Higher packaging densities
 Reduced cost for function
 Extremely high reliability
 Suitability for operation
 Easy Replacement
4. List the Advantages of VLSI Technology?
Advantages:
1. Smaller size
2. Lower cost
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3. Lower power
4. Higher reliability
5. More functionality
6. Area Minimization
7. High Speed
5. What are the Disadvantages of VLSI Technology?
Disadvantages:
1. Long design and fabrication time
2. Higher risk to project
6. List the Uses of VLSI Technology
•Simplicity of operation.
•Occupies a relatively smaller silicon area.
•Manufacturing process is simple and requires only fewer processing steps.
•High component density (i.e., microprocessors and microcontrollers are
constructed).
•VLSI systems are High performance and cost effective systems.
•Consume less power than discrete components.
•Smaller in size.
•Easier to design and manufacture.
•Higher reliability.
•High operating speed.
•Design flexibility.
•High productivity
•Higher functionality.
•Design security.
7. Applications of VLSI
•Digital signal processing.
•Multimedia information systems-INTERNET
•Voice and data communication networks.
•Wireless LAN
•Reconfigurable computing
•Bus interface via PCI, USB
•Commercial electronics: TV sets, DVD.
•Computers and computer graphics.
•Auto mobiles, toys.
•Medicine: Hearing aids, implants for human body
8. Why low power has become an important issue in the present day VLSI
circuit realization?

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In deep submicron technology the power has become one of the most
important issues because of:
 Increasing transistor count: The number of transistors are getting
doubled in every 18 months based on Moore's Law
 Higher speed of operation: The power dissipation is proportional to the
clock frequency
 Greater device leakage currents: In nanometer technology the leakage
component becomes a significant percentage of the total power and the
leakage current increases at a faster rate than dynamic power in
technology generations
9. Explain Moore's Law
Moore’s Law:
In 1965, Gordon Moore, an industry pioneer, predicted that the number of
transistors on a chip was double every 18to 24 months. He also predict that
semiconductor technology will double its effectiveness every 18 months
 Many other factors also grow exponentially these are
– clock frequency
– processor performance
Increase in Transistor Count Moore’s Law: Number of transistors of a chip
doubles every 1.5 to 2 years

10. What is Level of Integration?

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It is a technique to increase number of devices per a chip.
11. Explain IC Technology or Discuss the Microelectronics evolutionary
process with examples.
The first integrated circuits held only a few devices, perhaps as many as ten
diodes, transistors, resistors, and capacitors, making it possible to fabricate
one or more logic gates on a single device. As on increasing the number of
components (or transistors) per integrated circuit the technology developed
as
Small scale integration(SSI): The technology was developed by integrating the
number of transistors of 1-100 on a single chip. Ex: Gates, flip-flops, op-amps.
Medium scale integration(MSI): The technology was developed by
integrating the number of transistors of 100-1000 on a single chip. Ex:
Counters, MUX, adders, 4-bit microprocessors.
Large scale integration(LSI) :The technology was developed by integrating the
number of transistors of 1000-10000 on a single chip. Ex:8-bit
microprocessors, ROM, RAM.
Very large scale integration(VLSI): The technology was developed by
integrating the number of transistors of 10000-1Million on a single chip.
Ex:16-32 bit microprocessors, peripherals, complimentary high MOS.
Ultra large scale integration(ULSI) :The technology was developed by
integrating the number of transistors of 1Million-10 Millions on a single chip.
Ex: special purpose processors.
Giant scale integration(GSI) :The technology was developed by integrating
the number of transistors of above 10 Millions on a single chip. Ex: Embedded
system, system on chip.
12. Compare speed and power performance of available technologies.

Over the past several years, Silicon CMOS technology has become the
dominant fabrication process for relatively high performance and cost
effective VLSI circuits. In order to improve on this throughput rate it 'Will be
necessary to improve the technology, both in terms of scaling and processing,
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and through the incorporation of other enhancements such as BiCMOS. In
particular, the emerging Gallium Arsenide(GaAs) based technology will be
most significant in this area of ultra high speed logic/fast digital processors.

Important and previous JNTU exam questions:

1. What are the Advantages and Disadvantages of VLSI Technology?
2. Explain Moore's Law? Explain its relevance with respect to evolution of IC
technology?
3. Explain IC Technology? or Explain about various IC technologies?[SET-
1,R13,Nov-2016] or Discuss the recent trends in IC technology?
4. What are the advantages of IC's over discrete components?
5.List the limitations of IC?
Assignment Questions:
1.Compare speed and power performance of available technologies.[SET-
2,R10,Jan-2014] [SET-1,R13,May-2017]
2. Discuss the Microelectronics evolutionary process with examples.[SET-
3,R10,Jan-2014]
3. Explain how the transistors are integrated on a single chip according to
Moore’s Law?[SET-1,R10,Jan-2014]
4. Explain the terms SSI LSI VLSI ULSI with the number of transistors per chip
and applications.[SET-1,R10,Apr-2016].

DAY-2
Topics to be covered:
 VLSI Design Flow

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1. Explain VLSI Design Flow

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a
series of steps, and eventually produces a packaged chip. A typical design
cycle may be represented by the flow chart shown in the Figure. Briefly
outline all the steps of the VLSI design cycle.
1. System Specification:
 The first step of any design process is to lay down the specifications of
the system. System specification is a high level representation of the
system. The factors to be considered in this process include:
performance, functionality, and physical dimensions (size of the die
(chip)). The fabrication technology and design techniques are also
considered.
 The specification of a system is a compromise between market
requirements, technology and economical viability. The end results are
specifications for the size, speed, power, and functionality of the VLSI
system.
2. Architectural Design:
 The basic architecture of the system is designed in this step. This
includes, decisions as RISC (Reduced Instruction Set Computer) versus
CISC (Complex Instruction Set Computer), number of ALUs, Floating
Point units, number and structure of pipelines, and size of caches among
others.
 The outcome of architectural design is a Micro-Architectural
Specification (MAS). While MAS is a textual (English like) description,
architects can accurately predict the performance, power and die size of
the design based on such a description.
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3. Behavioural or Functional Design:
 In this step, main functional units of the system are identified. This also
identifies the interconnect requirements between the units. The area,
power, and other parameters of each unit are estimated.
 The behavioural aspects of the system are considered without
implementing specific information. For example, it may specify that a
multiplication is required, but exactly in which mode such multiplication
may be executed is not specified. We may use a variety of multiplication
hardware depending on the speed and word size requirements. The key
idea is to specify behaviour, in terms of input, output and timing of each
unit, without specifying its internal structure.
 The outcome of functional design is usually a timing diagram or other
relationships between units. This information leads to the improvement
of the overall design process and reduction of the complexity of
subsequent phases. Functional or behavioural design provides quick
emulation of the system and allows fast debugging of the full system.
Behavioural design is largely a manual step with little or no automation
help available.
4. Logic Design:
 In this step the control flow, word widths, register allocation, arithmetic
operations, and logic operations of the design that represent the
functional design are derived and tested.
 This description is called Register Transfer Level (RTL) description. RTL is
expressed in a Hardware Description Language (HDL), such as VHDL or
Verilog. This description can be used in simulation and verification. This
description consists of Boolean expressions and timing information. The
Boolean expressions are minimized to achieve the smallest logic design
which conforms to the functional design. This logic design of the system
is simulated and tested to verify its correctness. In some special cases,
logic design can be automated using high level synthesis tools. These
tools produce a RTL description from a behavioural description of the
design.
5. Circuit Design:
 The purpose of circuit design is to develop a circuit representation based
on the logic design. The Boolean expressions are converted into a circuit
representation by taking into consideration the speed and power
requirements of the original design. Circuit Simulation is used to verify
the correctness and timing of each component.

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 The circuit design is usually expressed in a detailed circuit diagram. This
diagram shows the circuit elements (cells, macros, gates, transistors)
and interconnection between these elements. This representation is
also called a netlist. Tools used to manually enter such description are
called schematic capture tools. In many cases, a netlist can be created
automatically from logic (RTL) description by using logic synthesis tools.
6. Physical Design:
 In this step the circuit representation (or netlist) is converted into a
geometric representation. As stated earlier, this geometric
representation of a circuit is called a layout. Layout is created by
converting each logic component (cells, macros, gates, transistors) into a
geometric representation (specific shapes in multiple layers), which
perform the intended logic function of the corresponding component.
Connections between different components are also expressed as
geometric patterns typically lines in multiple layers.
 The exact details of the layout also depend on design rules, which are
the guidelines based on the limitations of the fabrication process and
the electrical properties of the fabrication materials. Physical design is a
very complex process and therefore it is usually broken down into
various sub-steps. Various verification and validation checks are
performed on the layout during physical design.
 In many cases, physical design can be completely or partially automated
and layout can be generated directly from netlist by Layout Synthesis
tools. Layout synthesis tools, while fast, do have an area and
performance penalty, which limit their use to some designs. Manual
layout, while slow and manually intensive, does have better area and
performance as compared to synthesized layout. However this
advantage may dissipate as larger and larger designs may undermine
human capability to comprehend and obtain globally optimized
solutions.
7. Fabrication:
 After layout and verification, the design is ready for fabrication. Since
layout data is typically sent to fabrication on a tape, the event of release
of data is called Tape Out. Layout data is converted (or fractured) into
photo-lithographic masks, one for each layer. Masks identify spaces on
the wafer, where certain materials need to be deposited, diffused or
even removed. Silicon crystals are grown and sliced to produce wafers.
Extremely small dimensions of VLSI devices require that the wafers be
polished to near perfection. The fabrication process consists of several
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steps involving deposition, and diffusion of various materials on the
wafer. During each step one mask is used. Several dozen masks may be
used to complete the fabrication process.
 A large wafer is 20 cm (8 inch) in diameter and can be used to produce
hundreds of chips, depending of the size of the chip. Before the chip is
mass produced, a prototype is made and tested. Industry is rapidly
moving towards a 30 cm (12 inch) wafer allowing even more chips per
wafer leading to lower cost per chip.
8. Packaging, Testing and Debugging:
 Finally, the wafer is fabricated and diced into individual chips in a
fabrication facility. Each chip is then packaged and tested to ensure that
it meets all the design specifications and that it functions properly. Chips
used in Printed Circuit Boards (PCBs) are packaged in Dual In-line
Package (DIP), Pin Grid Array (PGA), Ball Grid Array (BGA), and Quad Flat
Package (QFP). Chips used in Multi-Chip Modules (MCM) are not packed,
since MCMs use bare or naked chips.
Important and previous JNTU exam questions:
1. Explain VLSI Design flow steps.
DAY-3
Topics to be covered:
 MOS Transistors
 MOS Structure
1. What is MOS Transistor?
The MOS Transistor means: Metal-Oxide-Semiconductor Field Effect
Transistor which is the most basic element in the design of a large scale
integrated circuits(IC). These transistors are formed as a ``sandwich''
consisting of a semiconductor layer, usually a slice, or wafer, from a single
crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal.
These layers are patterned in a manner which permits transistors to be
formed in the semiconductor material (the ``substrate'') a diagram showing a
MOSFET is shown below in Figure .

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2. What are the types of MOS Transistors
With the Doping concentration of transistor, there are two types MOS
transistors
1. NMOS Transistor
2. PMOS Transistor
3. CMOS Transistor
3. What are the transistor modes of operations
They are classified as
1. Enhancement mode operation
2. Depletion mode operation
4. What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias is called enhancement
mode transistor i.e channel is not established and device is in a non
conducting condition, when VD=VS=VGS=0.

5. What is Depletion mode Device?

The Device that conduct with zero gate bias is called depletion mode device.
The channel may also be established so that it is present under the condition
VGS=0 by implanting suitable impurities in region between source and drain
during manufacturing process.

7. Explain the basic structure of a MOS transistor.

 NMOS devices are formed in a p-type substrate of moderate doping
level. The source and drain regions are formed by diffusing n-type
impurities to form depletion region. The depletion region mainly
extended in lightly doped p-region. Thus, source and drain are isolated
from one another by two diodes. Connections to the source and drain
are made by a deposited metal layer.
 The current through source and drain can be establishing and
controlling by any one of the two modes of nmos transistor.
 enhancement mode
 depletion mode transistors.
enhancement mode device: A polysilicon gate is deposited on a layer of
insulation over the region between source and drain.

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Fig shows a basic enhancement mode device in which the channel is not
established and the device is in a non-conducting condition, VD = VS = Vgs = 0. If
this gate is connected to a suitable positive voltage with respect to the
source, then the electric field established between the gate and substrate.
Because of this, there is charge inversion region in the substrate under the
gate insulation forming a conducting path or channel in between source and
drain.
The channel can also be established even at Vgs = 0 by implanting suitable
impurities in the region between source and drain during manufacture and
before to depositing the insulation at gate. This arrangement is shown in
Figure.

In depletion mode, source and drain are connected by a conducting channel,

the channel width can be controlled by applying a suitable negative voltage to
the gate. The variations of gate voltage allow control of any current flow
between source and drain.
The basic pMOS transistor structure for an enhancement mode device. In this
case the substrate is of n-type material and the source and drain diffusions
are consequently p-type.

In the figure, the application of a negative voltage of suitable magnitude (>

Vth) between gate and source will give rise to the formation of a p-type
channel between the source and drain. If the drain is made negative with
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respect to the source current will flow through channel. Here,the current is
carried by holes rather than electrons. In consequence, pMOS transistors are
inherently slower than nMOS, since hole mobility µp is less, by a factor of
approximately 2.5, than electron mobility µn·

6. Draw the detailed structure of NMOS transistor and explain the

enhancement mode transistor action.
NMOS Enhancement mode transistor
nMOS devices are formed in a p-type substrate of moderate doping level. The
source and drain regions are formed by diffusing n-type impurities through
suitable masks into these areas. Thus source and drain are isolated from one
another by two diodes and their Connections are made by a deposited metal
layer. The basic block diagrams of nMOS enhancement mode transistor is
shown in figure.

To understand the operation of transistor in enhancement mode, three

different conditions are considered. The fundamental requirement for
establishing a channel is application of Vt(threshold voltage) between gate
and source.
Condition 1: Vgs>Vt,Vds=0;

 If the gate terminal is connected to a positive voltage(a minimum

voltage level of threshold voltage) with respect to the source, then the
electric field established between the gate and the substrate which
gives a charge inversion region in the substrate under the gate
insulation and a conduction path or channel is formed between source
and drain, but no current flows between source and drain(Vds=0).
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Condition 2: Vgs>Vt, Vds<Vgs-Vt;

 When current flows in the channel by applying a voltage V ds between

source and drain there must be a voltage(IR) drop = V ds along the
channel. This results in the voltage between gate and channel varying
with distance along the channel with the voltage being a maximum of
Vgs at the source end.
 The effective gate voltage is Vg = Vgs - Vt .To invert the channel at the
drain end there will be voltage is available upto when Vds<Vgs-Vt. For all
voltages Vds < Vgs - Vt the device is in the non-saturated region.

Condition 3:Vgs>Vt, Vds>Vgs-Vt ;

• When Vds is increased to a level greater than V gs - Vt,, if the voltage drop
= Vgs - Vt takes place over less than the whole length of the channel near
the drain, there is insufficient electric field available to give rise to an

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inversion layer to create the channel. Then the voltage is called ‘pinch-
off’ voltage.
• At this stage the diffusion current completes the path from source to
drain and the channel exhibits a high resistance and behave as constant
current source, This region is known as ‘saturation’ region.
7. Draw the detailed structure of NMOS transistor and explain the depletion
mode transistor action.
nMOS Depletion mode transistor
The basic block diagram of nMOS Depletion Mode Transistor is shown in the
figure. In Depletion Mode Transistor the channel is established, Even the
voltage Vgs = 0 by implanting suitable impurities in the region between source
and drain during manufacture and prior to depositing the insulation and the
gate.

At this stage the source and drain are connected by a conducting channel, but
the channel may now be closed by applying a suitable negative voltage to the
gate. In both enhancement and depletion mode cases, variations of the gate
voltage allow control of any current flow between source and drain.

8. When is the channel is said to be pinched –off?

If a large Vds is applied this voltage with deplete the Inversion layer .This
Voltage effectively pinches off the channel near the drain.

Important and previous JNTU exam questions:

1. Draw the detailed structure of NMOS transistor and explain the
enhancement mode transistor action.[Jan2015/Set2] or Explain the MOS
transistor operation with the help of neat sketches in the Enhancement
mode.[SET-2,R13,Nov-2016].
2. Draw the detailed structure of NMOS transistor and explain the depletion
mode transistor action. [Jan2015/Set3] or Explain the MOS transistor
operation with the help of neat sketches in the Depletion mode.[SET-
3,R13,Nov-2016].
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3.Explain the MOS transistor operation with the help of neat sketches in the
following modes:
a)Enhancement Mode
b)Depletion Mode [SET-4 R05,NOV/DEC-2009]
4. Explain about MOS Structure
5. Explain the nMOS enhancement mode fabrication process for different
conditions of Vds?[SET-1,R13,MAR-2017]
Assignment Questions:
1. Explain the structure PMOS Depletion Transistor. [SET-3,4 R10,APR/MAY-
2013] [SET-2,R13,2015]
2.Explain the structure PMOS Enhancement Transistor[SET-1 R10,APR/MAY-
2013]
3.Explain the structure NMOS Enhancement Transistor [SET-2 R10,APR/MAY-
2013] [SET-1,R13,2014] [SET-4,R13,2015] [SET-3,R13,2017]

DAY-4
Topics to be covered:
 MOS transistor Fabrication Process
1. What are the most important process steps used in the semiconductor
fabrication
1. Oxidation
2. Lithography
3. Etching
4. Diffusion
5. Ion Implantation
6. Chemical Mechanical Planarization
2. Explain the following terms related to the fabrication of IC
(a) Lithography (b) oxidation (c) Ion Implantation (d) Diffusion
Lithography :
Lithography is used to transfer a pattern from a photomask to the surface of
the wafer. For example the gate area of a MOS transistor is defined by a
specific pattern. The pattern information is recorded on a layer of photoresist
which is applied on the top of the wafer. The photoresist changes its physical
properties when exposed to light (often ultraviolet) or another source of
illumination (e.g. X-ray). The photoresist is either developed by (wet or dry)
etching or by conversion to volatile compounds through the exposure itself.
The pattern defined by the mask is either removed or remained after
development, depending if the type of resist is positive or negative. For

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example the developed photoresist can act as an etching mask for the
underlying layers.
Oxidation:
Oxidation is a process which converts silicon on the wafer into silicon dioxide.
The chemical reaction of silicon and oxygen already starts at room
temperature but stops after a very thin native oxide film. For an effective
oxidation rate the wafer must be settled to a furnace with oxygen or water
vapor at elevated temperatures. Silicon dioxide layers are used as high-quality
insulators or masks for ion implantation. The ability of silicon to form high
quality silicon dioxide is an important reason, why silicon is still the
dominating material in IC fabrication.
Ion Implantation:
Ion implantation is the dominant technique to introduce dopant impurities
into crystalline silicon. This is performed with an electric field which
accelerates the ionized atoms or molecules so that these particles penetrate
into the target material until they come to rest because of interactions with
the silicon atoms. Ion implantation is able to control exactly the distribution
and dose of the dopants in silicon, because the penetration depth depends on
the kinetic energy of the ions which is proportional to the electric field. The
dopant dose can be controlled by varying the ion source. Unfortunately, after
ion implantation the crystal structure is damaged which implies worse
electrical properties. Another problem is that the implanted dopants are
electrically inactive, because they are situated on interstitial sites. Therefore
after ion implantation a thermal process step is necessary which repairs the
crystal damage and activates the dopants.
Diffusion :
Diffusion is the movement of impurity atoms in a semiconductor material at
high temperatures. The driving force of diffusion is the concentration
gradient. There is a wide range of diffusivities for the various dopant species,
which depend on how easy the respective dopant impurity can move through
the material. Diffusion is applied to anneal the crystal defects after ion
implantation or to introduce dopant atoms into silicon from a chemical vapor
source. In the last case the diffusion time and temperature determine the
depth of dopant penetration. Diffusion is used to form the source, drain, and
channel regions in a MOS transistor. But diffusion can also be an unwanted
parasitic effect, because it takes place during all high temperature process
steps.
3. Explain about process of Oxidation?

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Silicon is the most popular semiconductor for IC fabrication because of its
native oxide Sio2.Sio2 has excellent insulating properties. A very good quality
oxide can be grown on the Si substrate.
Important uses of Sio2:
 Sio2 act as protecting buffer layer during device fabrication
 it is used for device isolation
 it is used in the MOSFET device(gate oxide)
 it is used for interconnected isolation(Field oxide)
Oxidation is the process of growing the Sio2 layer on top of the Si substrate.
There are different types of oxidation techniques:
1. Thermal Oxidation
2. high pressure oxidation
3. plasma oxidation
Thermal Oxidation:
The oxidation process starts from the top surface of the Si wafer & it slowly
penetrates into the wafer. The separation line between the Si substrate &
the grown Sio2 layer is layer is known as the Si-Sio2 interface.
The quality of oxide & the Si-Sio 2 interface interface greatly influence the
behaviour of the MOSFET device.

The formation of silicon dioxide (Sio2) on silicon surface is accomplished

through thermal oxidation process. The thermal oxidation process requires
extremely high temperature between 700 to 1200° C.
A)Dry Oxidation: In this process silicon substrate is exposed to high purity
oxidation species such as oxygen gas i.e dry oxidation. Si + O 2↑→Sio2
reaction takes place in the temperature range 900 to 1200° C. Dry
Oxidation is straight forward using microprocessor controlled equipment.
B)Wet Oxidation: In this technique wet oxidation takes place by using
water vapor which is reacted with the Si layer & the reaction is expressed
as Si + 2H2O↑ → Sio2 + 2H2↑.wet oxidation can be carried out
conveniently by the phylogenic technique which reacts H 2 & O2 to form
water vapor.
High Pressure Oxidation:

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High pressure oxidation of silicon is particularly attractive became thermal
oxide layers can grow at relatively low temperatures in run times
comparable to typical high temperature 1 atm conditions. High
temperature and high pressure oxidations reduced the oxidation time. It
has been need mostly in bipolar applications, in MOS application has been
successfully, made to the growth of a thick field oxide layer in dynamic
RAM. Used the 1100°C temperature for 25 atm pressure.
Plasma Oxidation:
This process offers the possibility of growing high quality oxides at
temperature even lower than those achieved with high pressure
technique. This process has all the advantages associated with low
temperature processing. It is a low temperature vacuum process, usually
carried out in a pure oxygen discharge.
4.Expalin about lithography process?
Lithography is the process of transferring patterns of geometric shapes on
a mask to a thin layer of radiation sensitive material known as resist cover.
Pattern includes the implantation regions, contact regions bonding pad
etc..Resist patterns are also transferred into the underlying layers, after
transferring the pattern etching is done to remove unmasked portions of
the layers.
The exposing radiations are transferred through clean part of the mask.
The exposing radiations are UV rays, electronics, X-rays or ions.
Photolithography is the technology to create a pattern on the silicon wafer
using an UV ray of light.

The basic steps involved in the photo lithography process:

1. Si wafer 2. Photo resist 3. prebaking of photo resist or lens

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4.mask transfer with the desired pattern 5. UV light source & method of
projecting the image of the mask onto the photo resist 6. Selectively
removing it from the regions where it was exposed 7. Negative
photoresist 8. Positive photoresist

The mask has certain regions transparent & other regions un-transparent.
The transparent region of the mask allow the UV light to pass through &fall
on the photoresist. If photoresist is positive or negative it undergoes some
chemical changes & becomes more soluble or less soluble in an etchant
solution. For positive photoresist the pattern is same as the mask & for
negative photoresist the pattern is inverter mask.
Types of lithography:
1. Optical lithography or Photo lithography: Uses UV light.
2. Electron beam lithography: Uses electron beam, can generate micron &
submicron resist geometric in a highly automated & precisely controlled
environment.
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3. X-ray lithography: Uses X-ray wavelengths, so diffractions effects are
reduced & highest resolution is achieved.
4.Ion beam lithography: Uses from an ion source high degree of resolution
as compared to other lithographic techniques.
5.Discuss about Probe testing?
Testing the individual die at the wafer level is called probe. This is direct
approach for un-encapsulated semiconductor dies. Testing at the wafer
level is done for two purposes:
1. To detect the bad die
2. To save on the cost of packaging faulty devices.
In the probing process, the wafer is carefully mounted onto a movable
plate. The wafer can be removed either manually or automatically by the
machine in both vertical & horizontal directions.
The electronic connection is made via s probe card. A probe card is a
printed circuit board(PCB) designed to match the bonding pad. The test
program is run to determine the pass/fail status of the die.
After a die is tested, the wafer is the moved into position for the next die to
the tested.
A known good die(KGD) can be:
1.Packaging for end user in some types of custom package
2. Mounted directly on a substrate
3. Combined with other died in a multi chip package(MCP)

Important and previous JNTU exam questions:

1. Explain the following terms related to the fabrication of IC [Nov2008]
(a) Diffusion (b) oxidation (c) Lithography (d) Metallization. [SET-
1,R13,2014] [SET-2,R13,2016] [SET-1,R13,2017]
2. Explain the IC production process concept of oxidation and ion
implantation?[SET-4 R07,APR/MAY-2011].
3. Explain the processing steps used in IC fabrication process? or What are ic
fabrication steps.[SET-1,R10,Nov-2016] or Explain different steps involved in
the IC fabrication?[SET-4,R13,Nov-2016].
4.With neat sketches necessary, explain the oxidation process in IC fabrication
process[SET-3 R05,APR/MAY-2011].

DAY-5
Topics to be covered:
 nMOS Fabrication Process

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1. What are the basic steps in n-MOS fabrication process? Explain them with
diagrams.
NMOS FABRICATION
Fabrication is the process to create the devices and wires on a single silicon
chip.
• The process starts with a silicon substrate of high purity into which the
required p-impurities are introduced.

• A layer of silicon dioxide(sio2) is grown all over the surface of the wafer
to protect the surface and acts as a barrier to dopants during processing
and provide a generally insulating substrate onto which other layers
may be deposited and patterned.

• The surface is now covered with a photo resist which is deposited onto
the wafer and spun to achieve an even distribution of the required
thickness.

• The photo resist layer is then exposed to ultraviolet light through a mask
which defines those regions into which diffusion is to take place together
with transistor channels.

 These areas are subsequently readily etched away together with the
underlying silicon dioxide so that the wafer surface is exposed in the
window defined by the mask.

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 The remaining photoresist is removed and a thin layer of sio 2 is grown

over the entire chip surface and then poly silicon is deposited on top of
this to form the gate structure.

 The polysilicon layer consists of heavily doped polysilicon deposited by

chemical vapour deposition(CVD).
 Further photoresist coating and masking allows the polysilicon to be
patterned and then the thin oxide is removed to exposed areas into which
n-type impurities are to be diffused to form the source and drain.

 Diffusion is achieved by heating the wafer to a high temperature and

passing a gas containing the desired n-type impurity over the surface.
• Thick oxide (sio2) is grown over all again and is then masked with photo
resist and etched to expose selected areas of the polysilicon gate and
the drain and source areas where connections area to be made.

• The whole chip then has metal deposited over the surface to a thickness
typically of 1µm. This metal layer is then masked and etched to form the
required interconnection pattern.

Problems: Class work

1. Draw the cross sectional view of nMOS Transistor
2. Draw the cross sectional view of pMOS Transistor
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Problems: Home work
1. Elaborate steps in pMOS fabrication process with suitable sketch?[SET-
3,R10,May-2015]
Important and previous JNTU exam questions:
1. What are the basic steps in n-MOS fabrication process? Explain them with
diagrams. [May2014/set2] .[Jan 2015/Set1/Set3] or Explain the fabrication
steps for NMOS technology with neat diagrams? [SET-3,R10,APR/MAY-2015]
[SET-4,R07,APR/MAY-2011] [SET-1,R13,2014] [SET-4,R13,2015] [SET-
3,R13,2017] or
With neat sketches explain the nmos fabrication
procedure[SET-1,R10,NOV/DEC-2016]
2. Explain the various steps in PMOS fabrication. [May2014/set2],
.[Jan2015/Set2] [SET-2,R10,2016] [SET-3,R13,2017]
3.Explain the various fabrication steps for PMOS technology with neat
diagrams?[SET-4,R10,APR/MAY-2015]
DAY-6
Topics to be covered:
 CMOS fabrication process
 SOI Fabrication Process
1. What are the different types of CMOS process?
p-well process
n-well process
Twin- tub Process
Silicon-On-Insulator Process
2. With neat diagrams, explain the different steps in n-well fabrication of
CMOS transistors. (or)
Explain the CMOS fabrication process with neat sketches.
The CMOS can be fabricated using different processes such as:
 N-well process for CMOS fabrication
 P-well process
 Twin tub-CMOS-fabrication process
The fabrication of CMOS can be done by following the below shown twenty
steps, by which CMOS can be obtained by integrating both the NMOS and
PMOS transistors on the same chip substrate. For integrating these NMOS
and PMOS devices on the same chip, special regions called as wells or tubs are
required in which semiconductor type and substrate type are opposite to
each other.

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A P-well has to be created on a N-substrate or N-well has to be created on a
P-substrate. In this article, the fabrication of CMOS is described using the P-
substrate, in which the NMOS transistor is fabricated on a P-type substrate
and the PMOS transistor is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows:
Step1: Substrate
Primarily, start the process with a P-substrate.

Step2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen,
which are exposed in an oxidation furnace approximately at 1000 degree
centigrade.

Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as
Photoresist layer. It is formed.

Step4: Masking
The photoresist is exposed to UV rays through the N-well mask

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Step5: Photoresist removal
A part of the photoresist layer is removed by treating the wafer with the basic
or acidic solution.

Step6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the
removal of photoresist using hydrofluoric acid.

Step7: Removal of photoresist

The entire photoresist layer is stripped off, as shown in the below figure.

Step8: Formation of the N-well

By using ion implantation or diffusion process N-well is formed.

Step9: Removal of SiO2

Using the hydrofluoric acid, the remaining SiO2 is removed.

Step10: Deposition of polysilicon

Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer
of gate oxide.

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Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and
PMOS, the remaining layer is stripped off.

Step12: Oxidation process

Next, an oxidation layer is formed on this layer with two small regions for the
formation of the gate terminals of NMOS and PMOS.

Step13: Masking and N-diffusion

By using the masking process small gaps are made for the purpose of N-
diffusion.

The n-type (n+) dopants are diffused or ion implanted, and the three n+ are
formed for the formation of the terminals of NMOS.

Step14: Oxide stripping

The remaining oxidation layer is stripped off.

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Step15: P-diffusion
Similar to the above N-diffusion process, the P-diffusion regions are diffused
to form the terminals of the PMOS.

Step16: Thick field oxide

A thick-field oxide is formed in all regions except the terminals of the PMOS
and NMOS.

Step17: Metallization
Aluminum is sputtered on the whole wafer.

Step18: Removal of excess metal

The excess metal is removed from the wafer layer.

Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps.

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Step20: Assigning the names of the terminals of the NMOS and PMOS

2. List main processing steps in N-well CMOS fabrication

3. Draw the cross sectional view of N-well CMOS?

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Problems: Class work

1. Fabrication of CMOS using P-well process
Summary steps for P-well Process:

2. Draw the Cross sectional view of CMOS Transistor

Important and previous JNTU exam questions:
1. List main processing steps in N-well CMOS fabrication
2.With neat diagrams, explain the different steps in n-well fabrication of
CMOS transistors. [May2014/set1] (or) Explain the CMOS fabrication process
with neat sketches.[Jan2015/Set1] or Discuss the steps involved in N – well
CMOS process [SET-2,R10,APR/MAY-2013] or Explain the various fabrication
steps for CMOS technology with neat diagrams.[SET-2,R10,JAN-2014]
3. Fabrication of CMOS using P-well process or Discuss the steps involved in P
– well CMOS process[SET-1,R10,APR/MAY-2013] or With neat sketches
explain CMOS fabrication using p-well process?[SET-1,R10,APR-2017]
DAY-7
Topics to be covered:
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 Twin tub fabrication process
 SOI Fabrication Process
1. What are the steps involved in twin-tub process?
 Tub Formation
 Thin-oxide Construction
 Source & Drain Implantation
 Contact cut definition
 Metallization.
2. List different steps of the CMOS fabrication using the twin tub process
Different steps of the CMOS fabrication using on the twin tub process are as
follows:
 Lightly doped n+ or p+ substrate is taken and, to protect the latch up,
epitaxial layer is used.
 The high-purity controlled thickness of the layers of silicon are grown
with exact dopant concentrations.
 The dopant and its concentration in Silicon are used to determine
electrical properties.
 Formation of the tub
 Thin oxide construction
 Implantation of the source and drain
 Cuts for making contacts
 Metallization

3. What are the advantages of twin tub process?

Advantages of twin tub process are
1) Separate optimized wells are available.
2) Balanced performance is obtained for n and p transistors.
4. What is SOI? What is the material used as insulator?
SOI means Silicon–on-Insulator. In this process, sapphire or sio2 is used as
insulator
5. Silicon-on-Insulator (SOI) CMOS Processing steps
Silicon on insulator (SOI) CMOS processes has several potential advantages
such as higher density, no latch-up problems, and lower parasitic
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capacitances. In the SOI process a thin layer of single crystal silicon film is
epitaxial grown on an insulator such as sapphire or magnesium aluminates
spinal. The steps involves are:
1) A thin film (7-8 μm) of very lightly doped n-type Si is grown over an
insulator (Fig a). Sapphire is a commonly used insulator.

2) An anisotropic etch is used to etch away the Si (Fig b) except where a

diffusion area will be needed.

3) The p-islands are formed next by masking the n-islands with a photoresist.
A p-type dopant (boron) is then implanted. It is masked by the photoresist
and at the unmasked islands. The p-islands (Fig c) will become the n-channel
devices.

4) The p-islands are then covered with a photoresist and an n-type dopant,
phosphorus, is implanted to form the n-islands (Fig d). The n-islands will
become the p-channel devices.

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5) A thin gate oxide (500-600Å) is grown over all of the Si structures (Fig e).
This is normally done by thermal oxidation.

6) A polysilicon film is deposited over the oxide.

7) The polysilicon is then patterned by photomasking and is etched. This
defines the polysilicon layer in the structure as in Fig f.

8) The next step is to form the n-doped source and drain of the n-channel
devices in the p-islands. The n-island is covered with a photoresist and an n-
type dopant (phosphorus) is implanted (Fig g).

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9) The p-channel devices are formed next by masking the p-islands and
implanting a p-type dopant. The polysilicon over the gate of the n-islands will
block the dopant from the gate, thus forming the p-channel devices is shown
in Fig h.

10) A layer of phosphorus glass is deposited over the entire structure. The
glass is etched at contact cut locations. The metallization layer is formed. A
final passivation layer of a phosphorus glass is deposited and etched over
bonding pad locations.
6. What are the advantages and disadvantages of SOI process?
Advantages of SOI process
There is no well formation in this process
There is no field –Inversion problem.
There is no body effect problem.
Disadvantages of SOI process
It is very difficult to protect inputs in this process.
Device gain is low.
The coupling capacitance between wires always exists.
7. Compare the BiCMOS and CMOS technologies.
CMOS Technology
It is a complementary of MOS technology or CSG (Commodore Semiconductor
Group) which was started as source for manufacturing the electronic
calculators. After that complementary of MOS technology called CMOS
technology is used for developing the integrated circuits such as digital logic
circuits along with microcontrollers and microprocessors. CMOS technology
affords benefit of less power dissipation and low noise margin with high
packing density.

CMOS CD74HC4067

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The figure shows the utilization of CMOS technology in manufacturing the
digital controlled switch devices.
Bipolar Technology
Bipolar transistors are part of integrated circuits and their operation is based
on two types of semiconductor material or depends on both types of charge
carriers holes and electrons.These are generally classified into two types as
PNP and NPN,classified based on doping of its three terminals and their
polarities. It affords high switching as well as input/output speed with good
noise performance.

Bipolar AM2901CPC

The figure shows the utilization of bipolar technology in RISC processor

AM2901CPC.
Problems: Class work
1. Draw the cross sectional view of twin tub CMOS process
2. Draw the cross sectional view of SOI process

3. What are the advantages of SOI technology

 Due to the absence of wells, denser structures than bulk silicon can be
obtained.
 Low capacitances provide the basis of very fast circuits.
 No field-inversion problems exist.

 No latch-up due to isolation of n- and p- transistors by insulating

substrate.
 As there is no conducting substrate, there are no body effect problems
 Enhanced radiation tolerance.
Problems: Home work
1. Draw the SOI fabrication processing steps.
Important and previous JNTU exam questions:
1. Compare the BiCMOS and CMOS technologies.[Jan2015/Set4]
2. Draw the cross sectional view of SOI process
3. Draw the cross sectional view of twin tub CMOS process

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4. Draw the SOI fabrication process steps?
5. Discuss the steps involved in Twin Tub CMOS process.
[SET-3,R10,APR/MAY-2013]
or Explain the fabrication steps of twin-tub process for CMOS technology.
[SET-4,R10,JAN-2014]
or Explain the steps in twin-tub process of CMOS fabrication with suitable
sketch.[SET-4,R10,MAY-2015]
6. What are the advantages of SOI?[SET-1,R10,APR-2017]

DAY-8
Topics to be covered:
 Difference between BiCMOS and CMOS
 BiCMOS Fabrication Process
1. What are the advantages of BICMOS Technology over CMOS Technology?
Advantages of BiCMOS technology
 Analog amplifier design is facilitated and improved by using high
impedance CMOS circuit as input and remaining are realized by using
bipolar transistors.
 BiCMOS is essentially vigorous to temperature and process variations
offering good economical considerations (high percentage of prime
units) with less variability in electrical parameters.
 High load current sinking and sourcing can be provided by BiCMOS
devices as per requirement.
 Since it is a grouping of bipolar and CMOS technologies we can use BJT if
speed is a critical parameter and we can use MOS if power is a critical
parameter and it can drive high capacitance loads with reduced cycle
time.
 It has low power dissipation than bipolar technology alone.
 This technology found frequent applications in analog power managing
circuits and amplifier circuits such as BiCMOS amplifier.
 It is well appropriate for input/ouput intensive applications, offers
flexible inputs/outputs (TTL, CMOS and ECL).
 It has the advantage of improved speed performance compared to
CMOS technology alone.
 Latch up invulnerability.
 It has the bidirectional capability (source and drain can be interchanged
as per requirement).

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Drawbacks of BiCMOS technology
 The fabrication process of this technology is comprised of both the
CMOS and bipolar technologies increasing the complexity.
 Due to increase in the complexity of the fabrication process, the cost of
fabrication also increases.
 As there are more devices, hence, less lithography.
2. Difference between CMOS and BiCMOS Technology

3. Draw the Fabrication process steps of BiCMOS transistor.

BiCMOS Logic
It is a complex processing technology that provides NMOS and PMOS
technologies amalgamated each other with the advantages of having very low
power consumption bipolar technology and high speed over CMOS
technology.MOSFETs grant high input impedance logic gates and bipolar
transistors provide high current gain.
4. Explain the Steps for BiCMOS Fabrication
The BiCMOS fabrication combines the process of fabrication of BJT and CMOS,
but merely variation is a realization of the base. The following steps show the
BiCMOS fabrication process.
Step1: P-Substrate is taken as shown in the below figure

P-substrate

Step2: The p-substrate is covered with the oxide layer

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Step3: A small opening is made on the oxide layer

Step4: N-type impurities are heavily doped through the opening

Step5: The P – Epitaxy layer is grown on the entire surface

Step6: Again, entire layer is covered with the oxide layer and two openings
are made through this oxide layer.

two openings are made through the oxide layer

Step7: From the openings made through oxide layer n-type impurities are
diffused to form n-wells

n-type impurities are diffused to form n-wells

Step8: Three openings are made through the oxide layer to form three active
devices.

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Three openings are made through the oxide layer to form three active devices
Step9: The gate terminals of NMOS and PMOS are formed by covering and
patterning the entire surface with Thinox and Polysilicon.

The gate terminals of NMOS and PMOS are formed with Thinox and
Polysilicon
Step10: The P-impurities are added to form the base terminal of BJT and
similar, N-type impurities are heavily doped to form emitter terminal of BJT,
source and drain of NMOS and for contact purpose N-type impurities are
doped into the N-well collector.

P-impurities are added to form the base terminal of BJT

Step11: To form source and drain regions of PMOS and to make contact in P-
base region the P-type impurities are heavily doped.

P-type impurities are heavily doped to form source and drain regions of PMOS
Step12: Then the entire surface is covered with the thick oxide layer.

Entire surface is covered with the thick oxide layer

Step13: Through the thick oxide layer the cuts are patterned to form the
metal contacts.

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The cuts are patterned to form the metal contacts

Step14: The metal contacts are made through the cuts made on oxide layer
and the terminals are named as shown in the below figure.

Metal contacts are made through the cuts and terminals are named
The fabrication of BICMOS is shown in the above figure with a combination of
NMOS, PMOS and BJT. In the fabrication process some layers are used such as
channel stop implant, thick layer oxidation and guard rings.
The fabrication will be theoretically difficult for including both the
technologies CMOS and bipolar. Parasitical bipolar transistors are produced
inadvertently is a problem of fabrication while processing p-well and n-well
CMOS. For the fabrication of BiCMOS many additional steps added for fine
tuning of bipolar and CMOS components. Hence, the cost of total fabrication
increases.
4. List n-well BiCMOS fabrication steps
The basic process steps used are those already outlined for CMOS but with
additional process steps and additional masks defining: (i) the p+ base region;
(ii) n+ collector area; and (iii) the buried subcollector (BCCD).

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Summary of BICMOS Fabrication:

Problems: Class work

1. Draw the cross sectional view of BiCMOS transistor
2. List n-well BiCMOS fabrication steps
3. What are the advantages of BICMOS process over CMOS technology?[SET-
4,R10,May-2015]
Important and previous JNTU exam questions:
1. What are the advantages of BICMOS Technology over CMOS Technology?
Nov2008 or What are the advantages of BICMOS process over CMOS
technology?[SET-4,R10,May-2015]
2. Draw the Fabrication process steps and cross section of BICMOS
transistor.Nov2008
3. List out the differences between CMOS and bipolar technologies.[SET-
1,R10,APR-2017] or List out Differences between CMOS and bipolar
technologies [SET-1.R10,DEC-2015] or Compare CMOS with bipolar
technologies.[SET-4,R13,NOV-2016] or Compare CMOS and Bipolar
technologies.[SET-4,R10,APR-2013]
4. With a neat sketch explain BICMOS fabrication in p-well process and also
explain its operation.[SET-1,R10,MAY-2015]
5.Compare BiCMOS and CMOS technologies.[SET-4,R10,JAN-2014]
6. Give the steps for single metal CMOS n-well process and additional steps
for bipolar devices. [SET-3,R10,May-2015].

DAY-9
Topics to be covered:
 Transistor regions of operation
 Transistor threshold voltage
1.Derive the relationship between DRAIN-TO-SOURCE CURRENT I DS versus
VOLTAGE VDS ?
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In the MOS transistor voltage on the gate is used to induce a charge in the
channel between source and drain. The charge is caused to move from source
to drain under the influence of an electric field created by voltage V DS applied
between drain and source. Since the charge induced is dependent on the
gate to source voltage Vgs, then Ids is dependent on both Vgs and VDS . Let us
consider the simplified structure of an nMOS transistor shown in Fig, in which
the majority carriers electrons flow from the source to the drain.

Now, transit time

= ( length of the channel) / (electron velocity) = L / v

Where velocity is given by the electron mobility and electric field;

where µ=electron or hole mobility(surface), and, EDS=electric

field(drain to source)

Now, EDS = VDS/ L, so that velocity

Thus, the transit time is

At room temperature (300 K), typical values of the electron and hole mobility
are given by

, and

THE NON –SATURATED REGION:-We shall derive the current-voltage

relationship separately for the linear (or non-saturated) region and the
saturated region of operation.

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Linear region : In this, the region of operation implies the existence of the
uninterrupted channel between the source and the drain, which is ensured
by the voltage relation VGS - Vth > VDS .

The voltage between the gate and the channel varies linearly with the
distance x from the source due to the IR drop in the channel. Assume that
the device is not saturated and the average channel voltage is VDS /2.

The effective gate voltage VG,eff = Vgs - Vth

Charge per unit area =

where Eg average electric field from gate to channel, : relative

permittivity of oxide between gate and channel (~4.0 for SiO2 ), and : free
space permittivity (8.85 x 10 -14 F/cm). So, induced charge .

where W: width of the gate and L : length of channel.

where D is the oxide thickness.

Thus, the current from the drain to the source may be expressed as

Thus, in the non-saturated region, where

where the parameter

Writing , where W/L is contributed by the geometry of the
device,

Since, the gate-to-channel capacitance is (parallel plate

capacitance), then

Denoting CG = C0 WL where C0 : gate capacitance per unit area,

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Saturated region : Under the voltage condition VGS - Vth = VDS , a MOS
device is said to be in saturation region of operation. In fact, saturation
begins when VDS = VGS - Vth , since at this point, the resistive voltage drop (IR
drop) in the channel equals the effective gate-to-channel voltage at the
drain. One may assume that the current remains constant as VDS increases
further. Putting VDS = VGS - Vth , the equations (2.2-2.5) under saturation
condition need to be modified as

The expressions derived for IDS are valid for both the enhancement and the
depletion mode devices. However, the threshold voltage for the nMOS
depletion mode devices (generally denoted as Vtd ) is negative .

Figure below depicts the typical current-voltage characteristics for nMOS

enhancement as well as depletion mode transistors. The corresponding
curves for a pMOS device may be obtained with appropriate reversal of
polarity.

Figure: Typical current-voltage characteristics for (a) depletion mode nMOS

transistors and (b) enhancement mode nMOS transistors.

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2. What is the threshold voltage of a MOS transistor? How it varies with the
body bias?
The gate structure of aMOS transistor consists, electrically, of charges stored
in the dielectric layers and in the surface to surface interfaces as well as in the
substrate itself.
Switching an enhancement mode MOS transistor from the off to the on state
consists in applying sufficicmt gate voltage to neutralize these charges and
enable the underlying silicon to undergo an inversion due to the electric field
from the gate.
Switching a depletion mode nMOS transistor from the on to the off state
consists in applying enough voltage to the gate to add to the stored charge
and invert the 'n' implant region to 'p'.
The threshold voltage V, may be expressed as:

Now, for polysilicon gate and silicon substrate, the value of <l>ms is negative
but negligible,and the magnitude and sign of V1 are thus determined by the
balance between the remaining negative term -Qss and the other two terms,
both of which are positive. To evaluate V1, each Co
term is determined as follows:

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3. What is body effect?

The increase the threshold voltage with increase in source and substrate
voltage is called body effect.

4. Explain body effect in detail

The body effects may also be taken into account since the substrate may be
biased with respect to the source, as shown in Figure

Increasing VsB causes the channel to be depleted of charge carriers and thus
the threshold voltage is raised.
Change in Vt is given by where is a constant which
depends on substrate doping so that the more lightly doped the substrate,
the smaller will be the body effect.

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Class Work:
1. An nMOS transistor is operating in active region with the following
parameters: VGS=4V,Vtn=0.6V,W/L=100,μnCox=90μA/V2. Find ID and RDS.
[SET-2,R10,May-2015]
2. An nMOS transistor is operating in non-saturation region with the following
parameters: VGS=5V,Vtn=0.7V,W/L=95,μnCox=90μA/V2. Find ID and RDS.
[SET-2,R10,May-2015]
Home Work:
1.Derive relation between IDS vs VDS.
2. Draw V-I characteristics of NMOS.
Previous JNTUK questions:
1. Derive an expression for MOS transistor threshold voltage.[SET-1,R10,Apr-
2013]
2. Derive an equation for relation of drain current and gate to source voltage
and drain to
source voltage for NMOS transistor.[SET-2,R10,Apr-2013] or Derive the
expression for drain current of a CMOS transistor.[SET-3 & 4
,R10,May-2014]
3. Draw the Ids-Vds characteristics and derive the relation between Ids and
W/L ratio.[SET-3,R10,Jan-2014]
4. Draw the structure of nMOS transistor and explain how Ids is depends on
W/L ratio.[SET-4,R10,Jan-2014]
5. Derive the expression for the threshold voltage of MOSFET.[SET-
1,R10,May-2014]
6. Explain effect of threshold voltage on MOSFET current equations.[SET-
1,R10,May-2015].
7. An nMOS transistor is operating in active region with the following
parameters: VGS=3.9V,Vtn=1V,W/L=100,μnCox=90μA/V2. Find ID and RDS.
[SET-2,R10,May-2015]
8. Define threshold voltages of a MOS device and explain its significance.[SET-
3,R10,May-2015]

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DAY-10

1. Derive the MOS TRANSISTOR TRANSCONDUCTOR g m AND OUTPUT

CONDUCTANCE gds ?
Transconductance expresses the relationship between output current Ids and
the input voltage.
V11 and is defined as

To find an expression for g,. in terms of circuit and transistor parameters,

consider that
the charge in channel Qc is such that

where 't is transit time. Thus change in current

Now

Then

but change in charge

so that ·

Now

In saturation

and substituting for

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Alternatively,

It is possible to increase the gm of a MOS device by increasing its width.

However, this will also increase the input capacitance and area occupied.
A reduction in the channel length results in an increase in ωo owing to the
higher gm.However, the gain of the MOS device decreases owing to the strong
degradation of the output resistance = l/gds·

The output conductance gd.s can be expressed by

Here the strong dependence on the channel length is demonstrated as

for the MOS device.

2. Explain about FIGURE OF MERIT of MOS Transistor
An indication of frequency response may be obtained from the parameter ѡ 0
where,

This shows that switching speed depends on gate voltage above threshold
and on carrier mobility and inversely as the square of channel length. A fast
circuit requires that gm be as high as possible.
Electron mobility on a (100) oriented n-type inversion layer surface (µn) is
larger than that on a ( 111) oriented surface, and is in fact about three times
as large as hole mobility on a (111) oriented p-type inversion layer. Surface
mobility is also dependent on the effective gate voltage (Vgs - Vt).
For faster nMOS circuits, then, one would choose a (100) oriented p-type
substrate in which the inversion layer will have a surface carrier mobility µn =
650 cm2/V sec at room temperature.

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2
Compare this with the typical bulk mobilities µn = 1250 cm /V sec, µp = 480
cm2/V sec from which it will be seen that µs/ µ = 0.5 (where µs = surface
mobility and µ =bulk mobility).
3. What is pass transistor?
The isolated nature of the gate allows MOS transistors to be used as switches
in series with lines carrying logic levels in a way that is similar to the use of
relay contacts. This application of the MOS device is called the pass transistor
and switching logic arrays can be formed-for example, an And array as in
Figure below.

4. General circuit structure of an nMOS inverter

 The driver transistor
– The input voltage Vin=VGS
– The output voltage Vout=VDS
– The source and the substrate are ground, VSB=0
 The load device
– Terminal current IL,
– Terminal voltage VL

5. Draw the Voltage transfer characteristic (VTC)

 The VTC describing Vout as a function of Vin under DC condition
 Very low voltage level
– Vout=VOH

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– nMOS off, no conducting current, voltage drop across the load is very
small, the output voltage is high
 As Vin increases
– The driver transistor starts conducting, the output voltage starts to
decrease
– The critical voltage point, dVout/dVin=-1
 The input low voltage VIL
 The input high voltage VIH
 Determining the noise margins
 Further increase Vin
– Output low voltage VOL, when the input voltage is equal to VOH
– The inverter threshold voltage Vth
Define as the point where Vin=Vout

6. What is pull down device?

A device connected so as to pull the output voltage to the lower supply
voltage usually 0V is called pull down device.
7. What is pull up device?
A device connected so as to pull the output voltage to the upper supply
voltage usually VDD is called pull up device.
8. Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared to PMOS
transistors.
9. Derive the pull-up to pull-down ratio (Zp.u}Zp.d.) for an nMOS inverter
driven by another nMOS inverter.
Consider the arrangement in Figure below in which an inverter is driven from
the output of another similar inverter. Consider the depletion mode transistor

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for which Vgs = 0 under all conditions, and further assume that in order to
cascade inverters without degradation of levels we are aiming to meet the
requirement

For equal margins around the inverter threshold, we set V;,v = 0.5 VDD· At
this point both
transistors are in saturation and

In the depletion mode

and in the enhancement mode

I=

Equating (since currents are the same) we have

where Wp.d.• Lp.d.• Wp.u.• and Lp.u. are the widths and lengths of the pull-
down and pull-up transistors respectively. Now write

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Now we can substitute typical values as follows:

Thus from the above equation

for an inverter directly driven by an inverter.

Home Work:
1.Derive Pull-up and pull down ration for nMOS inverter driven through nMOS
inverter.
2. Draw the circuit for nMOS inverter and explain its operation and
characteristics.
3.Derive transconductance.
Previous JNTUK questions:
1. Explain MOS transistor Figure of Merit.[SET-4,R10,Apr-2013]
2. Define the following terms:
( i ) Threshold voltage (ii) Body effect (iii) Figure of merit [SET-1,R10,Jan-2014]
3. ( a ) What is Threshold voltage and derive its expression.
( b) Derive the relation between pull-up and pull-down ratio for an nMOS
inverter driven by another nMOS inverter. [SET-2,R10,Jan-2014] [SET-
1,R10,Dec-2015]
4. Derive an equation for transconductance of an n-channel enhancement
MOSFET operating in active region.[SET-4,R10,May-2015]

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5. Explain the term output conductance, using necessary equations.[SET-
1,R13,Nov-2016]
6. Explain the figure of merit of a MOS transistor.[SET-2,R13,Nov-2016]
7. Derive the expression for the threshold voltage of MOSFET.[SET-3,R13,Nov-
2016]
8. Draw the circuit for nMOS inverter and explain its operation and
characteristics[SET-4,R13,Nov-2016]
9. a)Determine transconductance and output conductance ratio.
b) Define pass transistor. How the circuit is modeled for mos transistor?[SET-
1,R10,Apr-2016]
10. Derive an equation for transconductance of an n-channel enhancement
MOSFET operating in active region.[SET-1,R13,Mar-2017]

DAY-11

1. DERIVE PULL-UP TO PULL-DOWN RATIO FOR AN nMOS INVERTER DRIVEN

THROUGH ONE OR MORE PASS TRANSISTORS.
Now consider the arrangement of Figure 2.9 in which the input to inverter 2
comes from the output of inverter 1 but passes through one or more nMOS
transistors used as switches in series (called pass transistors).
We are concerned that connection of pass transistors in series will degrade
the logic1 level into inverter 2 so that the output will not be a proper logic 0
level. The critical condition is when point A is at 0 volts and B is thus at Vvv.
but the voltage into inverter 2 at point C is now reduced from V DD by the
threshold voltage of the series pass transistor.
With all pass transistor gates connected to Vvv (as shown in Figure),

there is a loss of V1P, however many are connected in series, since no static
current flows through them and there can be no voltage drop in the channels.
Therefore, the input voltage to inverter 2 is

Where

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We must now ensure that for this input voltage we get out the same voltage
as would be the case for inverter 1 driven with input = Vvv·
Consider inverter 1 with input = Vvv· If the input is at Vvv. then the ( p.d.
transistor T2 is conducting but with a low voltage across it; therefore, it is in
its resistive region represented by R 1 in Figure 2.10. Meanwhile, the p.u.
transistor T1 is in saturation and is represented as a current source.

For the p.d. transistor

Therefore

Note that V drt is small and V dstl2 may be ignored. Thus

Now, for depletion mode p.u. in saturation with Vgs = 0

Consider inverter 2 when input = VDD- Vtp. As for inverter 1

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If inv¢rter 2 is to have the same output voltage under these conditions then V
out 1 = V out 2.

Summarizing for an nMOS inverter:

• An inverter driven directly from the output of another should have a
Zp.ulZp.fl. ratio of ≥ 4/1.
• An inverter driven through one or more pass transistors should have a
Zp.u./Zp.d. ratio of≥ 8/1.

2. What are four possible alternatives of pull up.

The possible arrangements:
1. Load resistance RL (Figure 2.11 ). This arrangement is not often used
because of the large space requirements of resistors produced in a silicon
substrate.

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2. nMOS depletion mode transistor pull-up.
(a) Dissipation is high ,since rail to rail current flows when Vin = logical 1.
(b) Switchlng of output from 1 to 0 begins when Vin exceeds Vt, of p.d. device.
(c) When switching the output from 1 to 0, the p.u. device is non-saturated
initially and this presents lower resistance through which to charge capacitive
loads .

3. nMOS enhancement mode pull-up

(a) Dissipation is high since current flows when V;n =logical 1 (VaG is returned
to V00) .
(b) Vout can never reach V DD (logical I) if V GG = V 00 as is normally the case.
(c) VGG may be derived from a switching source, for example, one phase of a
clock,so that dissipation can be greatly reduced.
(d) If VGG is higher than VDD then an extra supply rail is required

4. Complementary transistor pull-up (CMOS)

(a) No current flow either for logical 0 or for logical 1 inputs.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions the p-channel is slower than the n-
channel device

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3. For a complex/compound CMOS logic gate, how do you realize the pull-up
and the pull-down networks?
A CMOS logic gate consists of a nMOS pull-down network and a pMOS pull-up
network. The nMOS network is connected between the output and the
ground, whereas the pull-up network is connected between the output and
the power supply. The nMOS network corresponds to the complement of the
function either in sum-of-product or product-of-sum forms and the pMOS
network is dual of the nMOS network .
Home work:
1. Derive the relation between pull-up and pull-down ratio for an nMOS
inverter driven through one or more pass transistors.
2.explain about the different alternative pull up forms.
Previous JNTUK questions:
1.Derive the relation between pull-up and pull-down ratio for an nMOS
inverter driven through one or more pass transistors.[SET-3,R10,Jan-2014]
2. Explain different forms of pull ups used as load in CMOS and in
enhancement and depletion modes of nMOS.[SET-2,R10,May-2015]
3. What are the alternate forms of pull up? Explain each.[SET-1,R13,Apr-2017]

DAY-12

1. Give the two possible topologies AND-OR-INVERT (AOI) and OR-AND-

INVERT (OAI) to realize CMOS logic gate.
The AND-OR-INVERT network corresponds to the realization of the nMOS
network in sum-of-product form. Where as the OR-AND-INVERT network
corresponds to the realization of the nMOS network in product-of-sum form.
In both the cases, the pMOS network is dual of the nMOS network .

2. Explain about CMOS Inverter.

The general arrangement and characteristics are illustrated in figure below.
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The current/voltage relationships for the MOS transistor

in the resistive region, or

in saturation. In both cases the factor K is a technology-dependent parameter

such that

The factor WIL is, of course, contributed by the geometry and it is common
practice to write

so that, for example

in saturation, and where β may be applied to both nMOS and pMOS

transistors as follows

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where Wn and Lm WP and LP are the n- and p-transistor dimensions

respectively.
The CMOS inverter has five distinct regions of operation.
Considering the static conditions first, it may be seen that in region 1 for
which Vi,. =logic 0, we have the p-transistor fully turned on while the n-
transistor is fully turned off.Thus no current flows through the _inverter and
the output is directly connected to V DD through the p-transistor. A good logic
1 output voltage is thus present at the output.
In region 5 Vin. = logic 1, the n-transistor is fully on while the p-transistor is
fully off.
Again, no current flows and a good logic 0 appears at the output.
In region 2 the input voltage has increased to a level which just exceeds the
threshold voltage of the n-transistor. The n-transistor conducts and has a
large voltage between source and drain; so it is in saturation. The p-transistor
is also conducting but with only a small voltage across it, it operates in the
unsaturated resistive region. A small current now flows through the inverter
from V00 to V55. If we wish to analyze the behavior in this region, we
equate the p-device resistive region current with the n-device saturation
current and thus obtain the voltage and current relationships.
Region 4 is similar to region 2 but with the roles of the p- and n-transistors
reversed.However, the current magnitudes in regions 2 and 4 are small and
most of the energy consumed in switching from one state to the other is due
to the larger current which flows in region 3.
Region 3 is the region in which the inverter exhibits gain and in which both
transistors are in saturation.
The currents in each device must be the same: smce the transistors are in
series, so

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from whence we can express V;n in terms of the β ratio and the other circuit
voltages and currents.

Since both transistors are in saturation, they act as current sources so that the
equivalent circuit in this region is two current sources in series between V00
and Vss with the output voltage coming from their common point. The region
is inherently unstable in consequence and the changeover from one logic
level to the other is rapid.
If βn = βP and if Vm = -VtP, then

This implies that the changeover between logic levels is symmetrically

disposed about the point at which

since only at this point will the two β factors be equal. But for βn = βP the
device geometries must be such that

Now the mobilities are inherently unequal and thus it is necessary for the
width to length ratio of the p-device to be two to three times that of the
n:.device, namely

However, it must be recognized that mobility µ is affected by the transverse

electric field in the ·channel and is thus dependent on Vgs It has been shown
empirically that the actual mobility is

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Ø is a constant approximately equal to 0.05, V1 includes any body effect, and
µz is the mobility with zero transverse field. Thus a β ratio of 1 will only hold
good around the point of symmetry when Vout = Vin = 0.5V·

3. Draw the circuit model of MOS transistor

The MOS transistor can be modeled with varying degrees of complexity.
However, a consideration of the actual physical construction of the device
leads to some understanding of the various components of the model.

CQc = gate to channel capacitance

Ccs = gate to source capacitance
CcD = gate to drain capacitance } Small for self-aligning nMOS process
Remaining capacitances are associated with the depletion layer and are
voltage dependent. Note that Css indicates source-to-substrate, CDs drain-to-
substrate, and Cs channel-to-substrate capacitances.
Home Work:
1. Explain about different regions of CMOS inverter.
JNTU previous questions:
1. For a CMOS inverter calculates the shift in transfer characteristic curve
when ᵝn/ᵝp ratio is varied from 1/1 to 10/1. [SET-2,R10,Dec 2015]

DAY-13
Topics to be covered:
 BiCMOS
 Latch-up in CMOS
1. Draw the BiCMOS inverter circuit and explain its working.
Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both
enhancement-type devices, OFF at Vin=0V)
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The MOS switches perform the logic function & bipolar transistors drive
output loads
Vin = 0 :
T1 is off. Therefore T3 is non-conducting
T2 ON - supplies current to base of T4
T4 base voltage set to Vdd.
T4 conducts & acts as current source to charge load CL towards Vdd.
Vout rises to Vdd - Vbe (of T4)
Note : Vbe (of T4) is base-emitter voltage of T4.
(pullup bipolar transistor turns off as the output approaches
5V - Vbe (of T4))
Vin = Vdd :
T2 is off. Therefore T4 is non-conducting.
T1 is on and supplies current to the base of T3
T3 conducts & acts as a current sink to discharge load CL towards 0V.
Vout falls to 0V+ VCEsat (of T3)
Note : VCEsat (of T3) is saturation V from T3 collector to emitter

Simplified BiCMOS Inventer

T3 & T4 present low impedances when turned on into saturation & load C L
will be charged or discharged rapidly
• Output logic levels will be good & will be close to rail voltages since
VCEsat is quite small & VBE » 0.7V. Therefore, inverter has high noise
margins
• Inverter has high input impedance, i.e., MOS gate input
• Inverter has low output impedance
• Inverter has high drive capability but occupies a relatively small area
• However, this is not a good arrangement to implement since no
discharge path exists for current from the base of either bipolar
transistor when it is being turned off, i.e.,
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• when Vin=Vdd, T2 is off and no conducting path to the base of T4
exists
• when Vin=0, T1 is off and no conducting path to the base of T3
exists
This will slow down the action of the circuit
2. What is the latch up problem that arises in bulk CMOS technology?
The latch-up is an inherent problem in both n-well as well as pwell based
CMOS circuits. The phenomenon is caused by the parasitic bipolar transistors
formed in the bulk of silicon as shown in the figure for the n-well process.
Latch-up can be defined as the formation of a low-impedance path between
the power supply and ground rails through the parasitic npn and pnp bipolar
transistors.
As shown the BJTs are cross-coupled to form the structure of a silicon-
controlled-rectifier (SCR) providing a short-circuit path between the power
rail and ground. Leakage current through the parasitic resistors can cause one
transistor to turn on, which in turn turns on the other transistor due to
positive feedback and leading to heavy current flow and consequent device
failure.
3. How can latch up problem can be overcome?
There are several approaches to reduce the tendency of Latch-up. Some of
the important techniques are mentioned below:
 Use guard ring around p- and/or n-well with frequent contacts to the
rings
 To reduce the gain product B1XB2
 Moving the n-well and the n+ source/drain further apart
 Buried n+ layer in well to reduce gain of Q1
 Higher substrate doping level to reduce R-sub
 Reduce R-well by making low resistance contact to GND
4. What are the benefits of SOI technology relative to conventional bulk
CMOS technology?
Benefits of SOI technology relative to conventional silicon (bulk CMOS):
 Lowers parasitic capacitance due to isolation from the bulk silicon,
which improves power consumption and thus high speed performance.
 Reduced short channel effects
 Better sub-threshold slope.
 No Latch up due to BOX (buried oxide).
 Lower Threshold voltage.
 Reduction in junction depth leads to low leakage current.
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 Higher Device density.
Problems: Class work
1. Design CMOS Inverter logic
2. Design NMOS Inverter logic
Home work:
1. Discuss Latch-up in CMOS and Bi-CMOS circuits.
2.Explain about different forms of Bi-CMOS inverter.
Important and previous JNTU exam questions:
1. How the latch up problem can be overcome?
2. Discuss Latch-up in CMOS and Bi-CMOS circuits.[SET-4,R10,Apr-2013]
3. Discuss about Bi CMOS inverter. or Explain how the BiCMOS inverter
performance can be improved. [SET-3,R10,Apr-2013] [SET-2,R13,Nov-2016]
4. What is Latchup in CMOS circuits? How to overcome it?[SET-4,R10,Jan-
2014] or Explain the latch-up phenomenon in CMOS circuits and the methods
by which that can be eliminated.[SET-1,R10,May-2014]
5. Explain Latch-up in CMOS circuits.[SET-1,R10,Dec-2015]
6. Explain latch up in CMOS circuits with neat sketches?[SET-1,R13,Apr-2017]

Raghu Engineering College Dept of ECE VLSI DESIGN Unit-I