Module 3

FET Amplifiers
Introduction, JFET Small Signal Model, JFET AC equivalent Circuit, Fixed-
Bias Configuration, Self-Bias Configuration (with bypassed Rs only),
Voltage- Divider Configuration, Source Follower Configuration.
BJT and JFET Frequency Response:
Introduction, General Frequency Considerations, Low Frequency Response
of BJT Amplifier, Low Frequency Response of FET Amplifier, Miller Effect
Capacitance, Multistage frequency effects.
• FET Amplifiers – Introduction
• Field-effect transistor amplifiers provide an excellent voltage gain with the
added feature of a high input impedance.
• They are also low-power-consumption configurations with good frequency
range and minimal size and weight.
• JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers having
similar voltage gains.
• The depletion MOSFET (MESFET) circuit, however, has a much higher input
impedance than a similar JFET configuration.
• The BJT has an amplification factor, β (beta), the FET has a transconductance
factor, gm
• The FET can be used as a linear amplifier or as a digital device in logic circuits.
• In fact, the enhancement MOSFET is quite popular in digital circuitry, especially
in CMOS circuits that require very low power consumption.
• FET devices are also widely used in high-frequency applications and in buffering
(interfacing) applications.
• The voltage gain of an FET amplifier is generally less than that obtained
using a BJT amplifier, the FET amplifier provides a much higher input
impedance than that of a BJT configuration.
• Output impedance values are comparable for both BJT and FET circuits.
• JFET SMALL-SIGNAL MODEL
• The ac analysis of a JFET configuration requires that a small-signal ac
model for the JFET be developed.
• A major component of the ac model will reflect the fact that an ac voltage
applied to the input gate-to-source terminals will control the level of
current from drain to source.
• The gate-to-source voltage controls the drain-to-source (channel)
current of a JFET.
• A dc gate-to-source voltage controls the level of dc drain current through
a relationship known as Shockley’s equation: ID = IDSS (1 – VGS/VP)2.
• The change in drain current that will result from a change in gate-to-
source voltage can be determined using the transconductance factor gm
in the following manner:
• The prefix trans - in the terminology applied to g m reveals that it
establishes a relationship between an output and an input quantity.
• The root word conductance was chosen because g m is determined by a
current-to-voltage ratio similar to the ratio that defines the conductance
of a resistor, G = 1/R = I/V.
• Solving for gm in Eq. (8.1), we have

• Graphical Determination of gm
• If we now examine the transfer characteristics of Fig. 8.1 , we find that gm
is actually the slope of the characteristics at the point of operation. That
is,
• Following the curvature of the
transfer characteristics, it is
reasonably clear that the slope and,
therefore, gm increase as we
progress from VP to IDSS .
• In other words, as VGS approaches 0
V, the magnitude of gm increases.
• Equation (8.2) reveals that gm can be
determined at any Q -point on the
transfer characteristics by simply
choosing a finite increment in VGS (or
in ID ) about the Q -point and then
finding the corresponding change in
ID (or VGS , respectively).
• The resulting changes in each
quantity are then substituted in Eq.
(8.2) to determine gm .
• Mathematical Definition of gm
• The graphical procedure just described is limited by the accuracy of the
transfer plot and the care with which the changes in each quantity can be
determined.
• Naturally, the larger the graph, the better is the accuracy, but this can
then become a cumbersome problem.
• An alternative approach to determe gm employs the following approach:
The derivative of a function at a point is equal to the slope of the
tangent line drawn at that point.
• If we therefore take the derivative of ID with respect to VGS (differential
calculus) using Shockley’s equation, we can derive an equation for gm as
follows:
• JFET Input Impedance Zi
• The input impedance of all commercially available JFETs is sufficiently
large to assume that the input terminals approximate an open circuit.
• In equation form,

• For a JFET a practical value of 109 (1000 MΩ) is typical, whereas a value
of 1012 Ω to 1015 Ω is typical for MOSFETs and MESFETs.
• JFET Output Impedance Zo
• The output impedance of JFETs is similar in magnitude to that of
conventional BJTs.
• On JFET specification sheets, the output impedance will typically appear
as gos or yos with the units of μS.
• The parameter yos is a component of an admittance equivalent circuit ,
with the subscript o signifying an output network parameter and s the
terminal ( source) to which it is attached in the model.
• For the JFET of Fig. 6.20 , gos has a range of 10μS to 50μS or 20 k (R = 1/G
= 1/50 μS) to 100 k (R = 1/G = 1/10 μS).
• In equation form,
• The output impedance is defined on the characteristics of Fig. 8.6 as the
slope of the horizontal characteristic curve at the point of operation.
• The more horizontal the curve, the greater is the output impedance.
• If it is perfectly horizontal, the ideal situation is on hand with the output
impedance being infinite (an open circuit)—an often applied
approximation.
• In equation form, Eq. (8.12)

• Note the requirement when applying Eq. (8.12) that the voltage VGS
remain constant when rd is determined.
• This is accomplished by drawing a straight line approximating the VGS line
at the point of operation.
• A ΔVDS or ΔID is then chosen and the other quantity measured off for use
in the equation.
• JFET AC Equivalent Circuit
• Now that the important parameters of
an ac equivalent circuit have been
introduced anddiscussed, a model for
the JFET transistor in the ac domain can
be constructed.
• The control of Id by Vgs is included as a
current source gmVgs connected from
drain to source as shown in Fig. 8.8 .
• The current source has its arrow
pointing from drain to source to
establish a 180° phase shift between
output and input voltages as will occur
in actual operation.
• The input impedance is represented by the open circuit at the input
terminals and the output impedance by the resistor rd from drain to
source.
• Note that the gate-to-source voltage is now represented by Vgs
(lowercase subscripts) to distinguish it from dc levels.
• In addition, note that the source is common to both input and output
circuits, whereas the gate and drain terminals are only in “touch” through
the controlled current source gmVgs.
• In situations where rd is ignored (assumed sufficiently large in relation to
other elements of the network to be approximated by an open circuit),
the equivalent circuit is simply a current source whose magnitude is
controlled by the signal Vgs and parameter gm —clearly a voltage-
controlled current source.
• FIXED-BIAS CONFIGURATION
• Now that the JFET equivalent circuit has
been defined, a number of fundamental
JFET small-signal configurations are
investigated.
• The approach parallels the ac analysis of
BJT amplifiers with a determination of the
important parameters of Zi , Zo and Av for
each configuration.
• The fixed-bias configuration of Fig. 8.10
includes the coupling capacitors C1 and C2
, which isolate the dc biasing arrangement
from the applied signal and load; they act
as short circuit equivalents for the ac
analysis.
• Once the levels of gm and rd are
determined from the dc biasing
arrangement, specification sheet, or
characteristics, the ac equivalent model
can be substituted between the
appropriate terminals as shown in Fig.
8.11 .
• Note that both capacitors have the
short-circuit equivalent because the
reactance XC = 1/(2πfC) is sufficiently
small compared to other impedance
levels of the network, and the dc
batteries VGG and VDD are set to 0V by a
short-circuit equivalent.
• The network of Fig. 8.11 is then
carefully redrawn as shown in Fig. 8.12
• Note the defined polarity of Vgs , which
defines the direction of gmVgs.
• If Vgs is negative, the direction of the
current source reverses.
• The applied signal is represented by Vi
and the output signal across RD|| rd by
Vo .
• Zi Figure 8.12 clearly reveals that

because of the infinite input impedance at the input terminals of the JFET.
• Zo Setting Vi = 0 V as required by the definition of Zo will establish Vgs as
0V also.
• The result is gmVgs = 0 mA, and the current source can be replaced by an
open-circuit equivalent as shown in Fig. 8.13 .
• The output impedance is
• If the resistance rd is sufficiently large (at least 10:1) compared to RD , the
approximation rd ||RD RD can often be applied and

• Av Solving for Vo in Fig. 8.12 , we find

• If
• Phase Relationship The negative sign in the resulting equation for Av
clearly reveals a phase shift of 180° between input and output voltages.
• SELF-BIAS CONFIGURATION
• Bypassed RS
• The fixed-bias configuration has the
distinct disadvantage of requiring
two dc voltage sources.
• The self-bias configuration of Fig.
8.15 requires only one dc supply.
• The capacitor CS across the source
resistance assumes its open-circuit
equivalence for dc, allowing RS to
define the operating point.
• Under ac conditions, the capacitor
assumes the short-circuit state and
“short circuits” the effects of RS .
• The JFET equivalent circuit is
established in Fig. 8.16 and carefully
redrawn in Fig. 8.17 .
• Since the resulting configuration is the
same as appearing in Fig. 8.12 , the
resulting equations for Z i , Zo , and Av
will be the same.
• VOLTAGE-DIVIDER CONFIGURATION
• The popular voltage-divider configuration for BJTs can also be applied to
JFETs as demonstrated in Fig. 8.21 .
• Substituting the ac equivalent model
for the JFET results in the
configuration of Fig. 8.22 .
• Replacing the dc supply VDD by a short-
circuit equivalent has grounded one
end of R1 and RD .
• Since each network has a common
ground, R1 can be brought down in
parallel with
• R2 as shown in Fig. 8.23 . RD can also
be brought down to ground, but in the
output circuit across rd .
• The resulting ac equivalent network
now has the basic format of some of
the networks already analyzed.
• Note that the equations for Zo and Av are the same as obtained for the fixed-bias
and self bias (with bypassed R S ) configurations.
• The only difference is the equation for Zi , which is now sensitive to the parallel
combination of R1 and R2 .
• SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION
• The JFET equivalent of the BJT emitter-follower configuration is the
source-follower configuration of Fig. 8.28 .
• Note that the output is taken off the source terminal and, when the dc
supply is replaced by its short-circuit equivalent, the drain is grounded
(hence, the terminology common-drain).
• Substituting the JFET equivalent circuit results in the configuration of Fig.
8.29 .
• The controlled source and the internal output impedance of the JFET are
tied to ground at one end and RS on the other, with Vo across RS .
• Since gmVgs, rd, and RS are connected to the same terminal and ground,
they can all be placed in parallel as shown in Fig. 8.30 .
• The current source reversed direction, but V gs is still defined between
the gate and source terminals.
• Zi Figure 8.30 clearly reveals that Z i is defined by

• Zo Setting Vi = 0 V results in the gate terminal being connected directly to

the ground as shown in Fig. 8.31 .
• The fact that Vgs and Vo are across the same parallel network results in
Vo = -Vgs.
• Av The output voltage V o is determined by
• Since the denominator of Eq. (8.43) is larger than the numerator by a
factor of one, the gain can never be equal to or greater than one (as
encountered for the emitter-follower BJT network).

• Phase Relationship Since Av of Eq. (8.43) is a positive quantity, Vo and Vi

are in phase for the JFET source-follower configuration.
 BJT and JFET Frequency Response
• Introduction
• The analysis thus far has been limited to a particular frequency.
• For the amplifier, it was a frequency that normally permitted ignoring the
effects of the capacitive elements, reducing the analysis to one that
included only resistive elements and sources of the independent and
controlled variety.
• We will now investigate the frequency effects introduced by the larger
capacitive elements of the network at low frequencies and the smaller
capacitive elements of the active device at high frequencies.
• Because the analysis will extend through a wide frequency range, the
logarithmic scale will be defined and used throughout the analysis.
• In addition, because industry typically uses a decibel scale on its
frequency plots, the concept of the decibel is introduced in some detail.
• GENERAL FREQUENCY CONSIDERATIONS
• The frequency of the applied signal can have a pronounced effect on the
response of a single-stage or multistage network.
• The analysis thus far has been for the midfrequency spectrum.
• At low frequencies, we shall find that the coupling and bypass capacitors
can no longer be replaced by the short-circuit approximation because of
the increase in reactance of these elements.
• The frequency-dependent parameters of the small-signal equivalent
circuits and the stray capacitive elements associated with the active
device and the network will limit the high-frequency response of the
system.
• An increase in the number of stages of a cascaded system will also limit
both the high- and low-frequency responses.
• Low-Frequency Range
• To demonstrate how the larger coupling and bypass capacitors of a
network will affect the frequency response of a system, the reactance of a
1-mF (typical value for such applications) capacitor is tabulated in Table
9.4 for a wide range of frequencies.
• Two regions have been defined in Table 9.4 .
• For the range of 10 Hz to 10 kHz the magnitude of the reactance is
sufficiently large that it may have an impact on the response of the
system.
• However, for much higher frequencies it appears as though the capacitor
is behaving much like the short-circuit equivalent it is designed to match.
• Clearly, therefore,
the larger capacitors of a system will have an important impact on the
response of a system in the low-frequency range and can be ignored for
the high-frequency region.
• High-Frequency Range
• For the smaller capacitors that come into play due to the parasitic
capacitances of the device or network, the frequency range of concern
will be the higher frequencies.
• Consider a 5-pF capacitor, typical of a parasitic capacitance of a transistor
or the level of capacitance introduced simply by the wiring of the
network, and the level of reactance that results for the same frequency
range appearing in Table 9.4 .
• The results appear in Table 9.5 and clearly reveal that at low frequencies
they have a very large impedance matching the desired open-circuit
equivalence.
• However, at higher frequencies they are approaching a short-circuit
equivalence that can severely affect the response of a network.
• Clearly, therefore,
the smaller capacitors of a system will have an important impact on the
response of a system in the high-frequency range and can be ignored for
the low-frequency region.
• Mid-Frequency Range
• In the mid-frequency range the effect of the capacitive elements is largely
ignored and the amplifier considered ideal and composed simply of
resistive elements and controlled sources.
• The result is that
the effect of the capacitive elements in an amplifier are ignored for the
mid-frequency range when important quantities such as the gain and
impedance levels are determined.
• Typical Frequency Response
• The magnitudes of the gain response curves of an RC -coupled, direct-
coupled, and transformer coupled amplifier system are provided in
Fig. 9.8 .
• Note that the horizontal scale is a logarithmic scale to permit a plot
extending from the low- to the high-frequency regions.
• For each plot, a low-, a high-, and a mid-frequency region has been
defined.
• In addition, the primary reasons for the drop in gain at low and high
frequencies have also been indicated within the parentheses.
• For the RC-coupled amplifier, the drop at low frequencies is due to the
increasing reactance of CC, Cs, or CE , whereas its upper frequency limit is
determined by either the parasitic capacitive elements of the network or
the frequency dependence of the gain of the active device.
• As indicated in Fig. 9.8 , the high-frequency response is controlled
primarily by the stray capacitance between the turns of the primary and
secondary windings.
• For the direct-coupled amplifier, there are no coupling or bypass
capacitors to cause a drop in gain at low frequencies.
• As the figure indicates, it is a flat response to the upper cutoff frequency,
which is determined by either the parasitic capacitances of the circuit or
the frequency dependence of the gain of the active device.
• For each system of Fig. 9.8 , there is a band of frequencies in which the
magnitude of the gain is either equal or relatively close to the midband
value.
• To fix the frequency boundaries of relatively high gain, 0.707Avmid was
chosen to be the gain at the cutoff levels.
• The corresponding frequencies f1 and f2 are generally called the corner,
cutoff, band, break, or half-power frequencies(HPF).
• The multiplier 0.707 was chosen because at this level the output power is
half the mid-band power output, that is, at mid-frequencies,
• LOW-FREQUENCY RESPONSE—BJT AMPLIFIER
WITH RL
• The analysis of this section will employ the loaded
( RL ) voltage-divider BJT bias configuration
introduced earlier in Section 9.6 .
• For the network of Fig. 9.25 , the capacitors Cs ,
CC, and CE will determine the low-frequency
response.
• We will now examine the impact of each
independently in the order listed.
• Cs Because Cs is normally connected between the
applied source and the active device, the general
form of the RC configuration is established by the
network of Fig. 9.26 with Ri = R1|| R2||βre.
• Applying the voltage-divider rule:
The impedance, expressed
in rectangular form

• The cutoff frequency defined by Cs can be determined by manipulating

the above equation into a standard form. Rewriting Eq. (9.29):
• At fLs the voltage Vb will be 70.7% of the mid band value assuming Cs is the
only capacitive element controlling the low-frequency response.
• For the network of Fig. 9.25 , when we analyze the effects of Cs we must
make the assumption that CE and CC are performing their designed
function or the analysis becomes too unwieldy, that is, that the
magnitudes of the reactances of CE and CC permit employing a short-
circuit equivalent in comparison to the magnitude of the other series
impedances.
• CC Because the coupling capacitor is normally connected between the
output of the active device and the applied load, the RC configuration that
determines the low-cutoff frequency due to CC appears in Fig. 9.27 . The
total series resistance is now Ro + RL, and the cutoff frequency due to CC is
determined by

• Ignoring the effects of Cs and CE , we find that the output voltage Vo will
be 70.7% of its midband value at fLC.
• For the network of Fig. 9.25 , the ac equivalent network for the output
section with Vi = 0V appears in Fig. 9.28 . The resulting value for Ro in Eq.
(9.32) is then simply
• CE To determine fLE, the network “seen” by CE must be determined as
shown in Fig. 9.29 .
• Once the level of Re is established, the cutoff frequency due to CE can be
determined using the following equation:

• For the network of Fig. 9.25 , the ac equivalent as “seen” by CE appears in

Fig. 9.30 as derived from Fig. 5.38 . The value of Re is therefore
determined by

• The effect of C E on the gain is best described in a quantitative manner by

recalling that the gain for the configuration of Fig. 9.31 is given by
• The maximum gain is obviously available where RE is 0 .
• At low frequencies, with the bypass capacitor CE in its “open-circuit” equivalent
state, all of RE appears in the gain equation above, resulting in the minimum
gain.
• As the frequency increases, the reactance of the capacitor CE will decrease,
reducing the parallel impedance of RE and CE until the resistor RE is effectively
“shorted out” by CE .
• The result is a maximum or midband gain determined by Av = -RC/re. At fLE the
gain will be 3 dB below the midband value determined with RE “shorted out.”
• Before continuing, keep in mind that Cs , CC , and CE will affect only the low-
frequency response.
• At the midband frequency level, the short-circuit equivalents for the capacitors
can be inserted.
• Although each will affect the gain Av = Vo/Vi in a similar frequency range, the
highest low-frequency cutoff determined by Cs , CC , or CE will have the greatest
impact because it will be the last encountered before the midband level.
• If the frequencies are relatively far apart, the highest cutoff frequency will
essentially determine the lower cutoff frequency for the entire system.
• If there are two or more “high” cutoff frequencies, the effect will be to
raise the lower cutoff frequency and reduce the resulting bandwidth of
the system.
• In other words, there is an interaction between capacitive elements that
can affect the resulting low-cutoff frequency.
• However, if the cutoff frequencies established by each capacitor are
sufficiently separated, the effect of one on the other can be ignored with
a high degree of accuracy—a fact that will be demonstrated by the
printouts to appear in the following example.
Since fLE >> fLC or fLS the bypass capacitor CE is determining the lower cutoff
frequency of the amplifier.
• MILLER EFFECT CAPACITANCE
• In the high-frequency region, the capacitive elements of importance are
the inter electrode (between-terminals) capacitances internal to the
active device and the wiring capacitance between leads of the network.
• The large capacitors of the network that controlled the low frequency
response are all replaced by their short-circuit equivalent due to their
very low reactance levels.
• For inverting amplifiers (phase shift of 180° between input and output,
resulting in a negative value for Av ), the input and output capacitance is
increased by a capacitance level sensitive to the inter electrode
capacitance between the input and output terminals of the device and
the gain of the amplifier.
• In Fig. 9.42 , this “feedback” capacitance is defined by Cf .
• establishing the equivalent network of Fig. 9.43 . The result is an
equivalent input impedance to the amplifier of Fig. 9.44 that includes the
same Ri that we dealt with in previous chapters, with the addition of a
feedback capacitor magnified by the gain of the amplifier.
• Any interelectrode capacitance at the input terminals to the amplifier
will simply be added in parallel with the elements of Fig. 9.43 .

• In general, therefore, the Miller effect input capacitance is defined by

• This shows us that:
For any inverting amplifier, the input capacitance will be increased by a
Miller effect capacitance sensitive to the gain of the amplifier and the
interelectrode (parasitic) capacitance between the input and output
terminals of the active device.
• The dilemma of an equation such as Eq. (9.49) is that at high frequencies
the gain Av will be a function of the level of CMi.
• However, because the maximum gain is the midband value, using the
midband value will result in the highest level of CMi and the worst-case
scenario.
• In general, therefore, the midband value is typically employed for Av in
Eq. (9.49).
• The reason for the constraint that the amplifier be of the inverting
variety is now more apparent when one examines Eq. (9.49).
• A positive value for Av would result in a negative capacitance (for Av > 1).
• The Miller effect will also increase the level of output capacitance, which
must also be considered when the high-frequency cutoff is determined.
• In Fig. 9.44 , the parameters of importance to determine the output
Miller effect are in place.
• Applying Kirchhoff’s current law results in

• The resistance Ro is usually sufficiently large to permit ignoring the first

term of the equation compared to the second term and assuming that
• Examples of the use of Eq. (9.50) appear in the next two sections as we
investigate the high-frequency responses of BJT and FET amplifiers.
For noninverting amplifiers such as the common-base and emitter-
follower configurations, the Miller effect capacitance is not a
contributing concern for high-frequency applications.
• MULTISTAGE FREQUENCY EFFECTS
• For a second transistor stage connected directly to the output of a first stage,
there will be a significant change in the overall frequency response.
• In the high-frequency region, the output capacitance Co must now include the
wiring capacitance (CW1), parasitic capacitance ( Cbe ), and Miller capacitance
(CMi) of the following stage.
• Furthermore, there will be additional low-frequency cutoff levels due to the
second stage, which will further reduce the overall gain of the system in this
region.
• For each additional stage, the upper cutoff frequency will be determined
primarily by the stage having the lowest cutoff frequency.
• The low-frequency cutoff is primarily determined by that stage having the
highest low-frequency cutoff frequency.
• Obviously, therefore, one poorly designed stage can offset an otherwise well-
designed cascaded system.
• The effect of increasing the number of identical stages can be clearly
demonstrated by considering the situations indicated in Fig. 9.58 .
• In each case, the upper and lower cutoff frequencies of each of the
cascaded stages are identical.
• For a single stage, the cutoff frequencies are f L and f H as indicated. For
two identical stages in cascade, the drop-off rate in the high- and low-
frequency regions has increased to -12 dB/octave or -40 dB/ decade.
• At f L and f H , therefore, the decibel drop is now 6 dB rather than the
defined band frequency gain level of -3 dB.
• The 3-dB point has shifted to f’L and f’H as indicated, with a resulting
drop in the bandwidth. A 18-dB/octave or 60-dB/decade slope will result
for a three-stage system of identical stages with the indicated reduction
in bandwidth ( f”L and f”H).
• Assuming identical stages, we can determine an equation for each band
frequency as a function of the number of stages ( n ) in the following
manner:
• For the low-frequency region,
• For the RC -coupled transistor amplifier, if fH = fb, or if they are close enough
in magnitude for both to affect the upper 3-dB frequency, the number of
stages must be increased by a factor of 2 when determining fH due to the
increased number of factors 1/(1 + jf/fx).
• A decrease in bandwidth is not always associated with an increase in the
number of stages if the midband gain can remain fixed and independent of the
number of stages.
• For instance, if a single-stage amplifier produces a gain of 100 with a
bandwidth of 10,000 Hz, the resulting gain−bandwidth product is 102 x 104 =
106.
• For a two-stage system the same gain can be obtained by having two stages
with a gain of 10 (10 x 10 = 100).
• The bandwidth of each stage would then increase by a factor of 10 to 100,000
due to the lower gain requirement and fixed gain−bandwidth product of 106.
• Of course, the design must be such as to permit the increased bandwidth and
establish the lower gain level.