CMOS DIGITAL VLSI DESIGN

CLOCKING STRATEGIES FOR SEQUENTIAL DESIGN V

SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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 Outline
• Introduction
• Latch-based clocking
• Slack borrowing
• Asynchronous design technique
• Self-Timed Pipelined Datapath
• Synchronizer
• Arbiter
• Recapitulation

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 Latch-Based Clocking

• In a latch based design combinational logic is separated

by transparent latches.
• Enables more flexible timing, allowing one stage to pass
slack to or steal time from following stages.
• Add logic circuit between latches of master-slave flip-flop.
• Overall performance is increased.
• Two phase clocking scheme is adopted.

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 Latch-Based Clocking
• On the falling edge of CLK1 (edge 2), A stable input is available to the combinational logic block A (CLB_A) .
• During the low phase of CLK1, CLB_A gets the computation time which is Tclk/2 .
• On the falling edge of CLK2, the output of CLB_A is latched.
• CLB_B computes on the low phase of CLK2 and the output is available on the falling edge of CLK1.
• The time available to perform the combination of CLB_A and CLB_B is TCLK.

Latch based design with timing diagram

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 Slack borrowing
Slack borrowing :
• The combinational logic blocks
are separated by level
sensitive latches, the
succeeding logic block can use
the time left over by the
preceding block.
• This approach requires no
explicit design changes, as the
passing of slack from one
block to the next is automatic.

Slack-borrowing in timing diagram

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 Asynchronous Design Technique
Problems in synchronous approach
• In reality ,because of the clock skew and jitter, all clock events don’t happen
simultaneously in a complete system.
• All the events occur at the clock edge, the overall current flow is very for these
significant of time. This causes noise problem due to presence of the power supply
resistance.
• The throughput rate of the pipelined system is directly linked to the worst-case
delay of the slowest element in the pipeline.

To overcome these problems, asynchronous design technique is adopted.

• Complete asynchronous system is very difficult to achieve because ensuring a
correct circuit operation that avoids all potential race conditions under any
operation condition and input sequence requires a careful timing analysis of the
network and extensive simulations in CAD tools.

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 Self-Timed Pipelined Datapath
• It is a reliable and robust technique which solves the local timing issue.
• A start signal initiates the computation of the logic block.
• Once the logic blocks finishes its computation, a Done flag is generated.
• Logic blocks must communicate with Acknowledge and Request signal.

Self-Timed Pipelined Datapath

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 Advantages of Self-Timed Circuit Design
• Separates the physical and logical ordering functions.
• Physical timing constraints are met with Done flag signal
• Though handshaking protocol the logical ordering is hold properly.
• Use of local timing signal instead of global clock distribution makes system to
operate faster.
• A self-timed circuit proceeds at the average speed of the hardware in contrast to
the worst-case model of synchronous logic.
• Power consumption overhead for distributing high speed clock is avoided in this
design technique.
• Robust by nature to the variation of manufacturing mismatch and temperature.

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 Self-Timed Adder Circuit
• The architecture is based on the
observation that the circuit delay of
the adder is dominated by the carry-
propagation path.

• The completion signal is efficiently

derived by combining the carry signals
of the different stages.

• The benefit of this approach is that

the completion generation starts
earlier and proceeds in parallel with
sum generation, which reduces the
critical timing path.

Source :Digital Integrated Circuits (2nd Edition)- Jan M. Rabaey Manchester-carry scheme with differential signal

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 Self-Timed Signaling
• A self-timed approach requires a handshaking Req

Ack
protocol to logically order the circuit.
• Sender and the receiver modules SENDER RECEIVER
Data
communicate each other by Req and Ack
signals.
Sender-receiver configuration
• Process steps
1. The sender places the data on the data bus.
2. The control signal Req changes its polarity by
the sender.
3. The receiver accepts the data when possible
and produces an event on the Ack signal.
4. After receiving the Ack signal, the sender
starts sending data for next stage.
• This process is called two phase protocol.

Timing Diagram

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 Two-phase handshake protocol

Data
Sender Logic Receiver logic
block block

A B Fn+1 Data ready Data accepted

A
0 0 0
c F 0 1 Fn
1 0 Fn Req
B C
1 1 1
Ack
(a) schematic (b) Truth table
Handshake logic

Muller C-element. Two-phase handshake protocol implemented with Muller C- element logic

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 Clock-Delayed Domino
• One application of self-timed circuits using the delay-matching concept is Clock-Delayed Domino,
where the clock for one stage is derived from the previous stage.
• Two inverter delays along the clock path emulate the worst case delay through the logic path
• Used in the IBM’s 1GHz Microprocessor and is used widely in high speed Domino logic.

Evaluate occurs Precharge occurs

CLK1 CLK2 CLK3 CLK4
C1

C2

Pulldown D2 Pulldown D3 Pulldown D4 Pulldown

out C3
D1
Network Network Network Network
C4

Phase2 Clk1

Clock Delayed Domino Logic with timing diagram

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 Synchronizer
• As the world is asynchronous in nature, The synchronous system has to
communicate with the world properly.
• The asynchronous signal must be resolved properly before fed into synchronous
system.
• The circuit that implements the decision-making function is called synchronizer.
• An asynchronous/synchronous interface is prone to errors called synchronization
failures.

Synchronous
Asynchronous system system

Synchronization

Interfacing synchronous system with asynchronous system

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 Synchronizer CLK
• During clock rising edge, the data is sampled.
• But there is violation of setup and hold time violation of latch as the
int
clock is not synchronized with the clock. D Q
• For this reason, waiting period is required.
• A signal is called undefined if its value is situated between VIH
• and VIL. CLK
I2
A simple synchronizer
Where, T = waiting period,
v(0)= range of value causes for the errors.

• The probability of v(0) for residing v(0) in the undefined region is VIH - VIL
Vswing
 VIH  VIL 
  tr (VIH – VIL)tr/Vswing
V
Pinit   
swing

Tsignal
tr
Linear approximation

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 Synchronizer
The synchronization error will increase if the clock frequency (φ) increases.
The average number of synchronization errors per second Nsync(0) if no synchronizer is used :
P
N sync (0)  init
T
where the sampling period.

The average number of synchronization errors with waiting period,

Pinit eT /  VIH  VIL  eT / tr

N sync (T)   
T  V
 swing  TsignalT

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 Arbiter
• An interlock element, or mutual exclusion circuit that decides which of the events will
occur first.
• For example multiple processor can access shared memory through arbiter.
• A synchronizer is a special arbiter in which one of its inputs tied to clock signal.

Req1

Req2
Res1
Res1 Ack1 A A VT gap

Ack1 B Ack2
Arbiter B
Res2 Ack2

Res2
Metastale
Ack1
Arbiter symbol
Arbiter circuit implementation Arbiter Timing Diagram

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 Recapitulation

• Latch based clocking technique uses latches between the logic blocks which improve improves
the overall performances.
• Latch is level sensitive, so the succeeding logic block can utilize the time left over by the
preceding logic block.
• Although there several advantages of using asynchronous system over synchronous system, but
designing a purely asynchronous circuit is a nontrivial and potentially hazardous task
• Self-timed design is an effective way for dealing with clock distribution, in which sender and
receiver communicate each other with request and acknowledge signal called handshaking
protocol.
• In order to make connection between synchronous and asynchronous circuit, arbiter and
synchronizer should be used to reduce the risk of synchronization errors.

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Thank You

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