EE-512: CMOS Analog IC Design
Lecture 1: Introduction to MOS transistor
August 29, 2017
Prepared by:
Ms. Vartika Verma
(under the supervision of Dr. Hitesh Shrimali)
A MOSFET as a switch
Figure 1 shows the symbol of an N-type metal oxide semiconductor field effect transistor
(MOSFET). The transistor is a three terminal device (for simplicity substrate connec-
tion is not considered). The source and drain terminals are interchangeable because of
symmetricity of the device. When operating as a switch, if the gate voltage VG is high
(higher than Vth ), the source and drain terminals are connected together. Whereas when
VG is low the drain and source are disconnected. This minimum voltage required to turn
ON the device is called as threshold voltage.
Gate
Source Drain
Figure 1: Symbol of N-type MOSFET.
The resistance between drain to source is dependent on the operation region of the MOS-
FET. The MOSFET operates in four regions viz. cutoff, linear, saturation and accumu-
lation region.
The limiting factor of speed is transit frequency (ft ) which is defined as the fre-
quency at which the small signal current gain of the device drops to unity while the
source and drain terminals are held at ground [1]. Further, it is assumed that transistor
has been DC biased and transit frequency gives the intrinsic (maximum) speed of the
MOSFET. That means, beyond this frequency the device cannot be used as a voltage
amplifier.
The MOSFET Structure
A simplified structure of an n-type MOS (NMOS) device is shown in figure 2. This
is fabricated on p-type substrate. The substrate is also known as body or bulk. The
NMOS device consists of two heavily doped n-regions which form the source and drain
terminals, and a heavily doped piece of poly-silicon, forming the gate terminal. There is
an insulating layer of SiO2 that isolates the gate from the substrate.
The path between the source and drain is called length (L) and that perpendicular to
the length is called width (W). During fabrication, the S/D junctions side-diffuse and the
actual distance between source and drain is slightly less than L. This distance is denoted
by Lef f .
Lef f = Ldrawn - 2LD
Where Ldrawn = total length and LD = amount of side diffusion
The substrate is the fourth terminal of the transistor that we ignored earlier. The device
characteristics are greatly influenced by substrate potential. In typical MOS operation
the S/D junction diodes must be reversed biased. The body/bulk of NMOS is connected
to most negative supply of the circuit while in the case of PMOS, it is connected to most
positive supply.
1
Figure 2: MOS transistor layout in 3D. [1]
Miscellaneous
Input-output impedances of various configurations:
Table 1: Impedances of various MOSFET configurations
Configuration Zin Zout
Voltage Controlled Voltage Source ∞ 0
(VCVS)
Current Controlled Current Source 0 ∞
(CCCS)
Current Controlled Voltage Source 0 0
(CCVS)
Voltage Controlled Current Source ∞ ∞
(VCCS)
Table 1 shows the input and output impedances associated with various amplifier topolo-
gies such as VCVS, CCCS, CCVS, VCCS. These topologies are commonly defined on the
basis of their impedances. Hence, the respective amplifier should be connected to the
respective impedance only. The changing of quantities in terms of impedance may create
loading effect. Sometimes, in case of insufficient power gain of the amplifier topology, the
voltage follower or buffer circuitry can be used.
Illustrations:
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Illustration 1: Find the output voltage if Vdd = 15V and Vss = -15V.
VDD
INPUT +
OUTPUT
Vref=2V −
VSS
Answer: 15V
Illustration 2: Define Pull Up and Pull Down Network.
Figure 3: Pull Up and Pull Down network.
Answer: Pull-up network - A network that provides a low resistance path to VDD ,
when output is logic ’1’ and provides a high resistance to VDD otherwise.
Pull-down network - A network that provides a low resistance path to ground when
output is logic ’0’ and provides a high resistance to ground otherwise.
If the pull down network is made using PMOS, then its gate terminal should be
provided with a negative voltage. Similarly, in an NMOS based pull up network, the
gate terminal should be provided with a voltage that is more positive than VDD . In such
a case, the voltage corresponding to logic states at input is different from that at the
output. Hence, two such ’CMOS’ gates cannot be interfaced directly. In other words,
VOH < VIH and VOL > VIL which will result in negative noise margin1 . And hence this
logic family would be incompatible with itself.
Illustration 3: What is the difference between large and small-signal ?
Answer: A small signal is one whose magnitude is of the order that the output voltage
after passing through amplifier stage still does not exceed the maximum swing possible.
A large signal is a DC signal that is one or more orders of magnitude larger than the
maximum value a small signal can take.It is used to analyze a circuit containing non-linear
components and to calculate its operating points (bias).
1
For more information regarding Noise Margin, Refer: Digital Integrated Circuits by Jan M. Rabaey,
Anantha Chandrakasan, Borivoje Nikolic
3
References
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. McGraw-Hill, 2001.
