Section A – Very Short Questions (2 Marks each)
Q1. Define combinational logic.
A combinational logic circuit is one in which the output depends only on the present
input values and not on past history. Example: Adders, MUX, Encoders.
Q2. Differentiate between half adder and full adder.
• Half adder: adds 2 inputs (A, B) → outputs SUM, CARRY.
• Full adder: adds 3 inputs (A, B, Cin) → outputs SUM, CARRY.
Q3. Write the Boolean expression of half subtractor.
• Difference (D) = A ⊕ B
• Borrow (Bo) = A'B
Q4. What is parity bit?
An extra bit added to data to detect errors. Even parity = total 1’s even; Odd parity =
total 1’s odd.
Q5. Write truth table of 2:1 multiplexer.
S I0 I1 Y
0 x x I0
1 x x I1
Section B – Short Questions (5 Marks each)
Q6. Explain the design procedure of a combinational circuit.
Answer:
1. Derive problem statement.
2. Make truth table.
3. Derive Boolean expression.
4. Simplify using K-map/Boolean algebra.
5. Draw logic diagram using gates.
Example: F(A,B,C)=Σm(1,2,4,7).
Q7. Derive expressions of Half Adder and draw circuit.
• SUM = A ⊕ B
• CARRY = A·B
Truth Table:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Circuit: XOR gate → SUM; AND gate → CARRY.
Q8. Write short note on Encoder and Decoder.
• Encoder: Converts 1-of-2ⁿ input into n-bit binary code. Example: 4-to-2 encoder.
• Decoder: Converts n-bit input into 1-of-2ⁿ outputs. Example: 2-to-4 decoder.
• Applications: Data compression, address decoding, etc.
Q9. Explain 1:4 De-multiplexer with truth table.
S1 S0 Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
Single input D routed to one output line depending on select lines.
Q10. Differentiate between PLA and PAL.
• PAL: Programmable AND array, Fixed OR array.
• PLA: Both AND and OR arrays programmable.
• PLA is more flexible; PAL is faster and cheaper.
Section C – Long / Problem Questions (10 Marks each)
Q11. Design a Full Adder.
• Inputs: A, B, Cin.
• Outputs: SUM, CARRY.
• Equations:
o SUM = A ⊕ B ⊕ Cin
o Cout = AB + BCin + ACin
• Truth Table:
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
• Implementation: Two half adders + OR gate.
Q12. Design Half Subtractor and Full Subtractor.
• Half Subtractor:
o D=A⊕B
o Bo = A'B
• Full Subtractor:
o D = A ⊕ B ⊕ Bin
o Bout = A'B + B·Bin + A'·Bin
Truth tables can be drawn (similar to adder).
Q13. Implement Boolean function using 8:1 MUX.
Example: F(A,B,C) = Σm(1,2,5,7).
• Select lines: A,B,C.
• Place 1 at I1, I2, I5, I7; others 0.
• Output Y = F(A,B,C).
Q14. Explain parity generator and parity checker with example.
• Parity Generator: For 3-bit data, even parity bit P = A ⊕ B ⊕ C.
• Parity Checker: Received (A,B,C,P). Check = A ⊕ B ⊕ C ⊕ P. If result = 0 → no
error; else → error.
Q15. Explain Code Conversion with example.
• Binary → Gray (4-bit):
o G3 = B3
o G2 = B3 ⊕ B2
o G1 = B2 ⊕ B1
o G0 = B1 ⊕ B0
Example: Binary 1011 → Gray 1110.
• Gray → Binary (reverse XOR method).
