925 DSG

High Resolution Delta-Sigma ADCs

Slide 1

Agenda
A/D Conversion Basics High Resolution ADC Architectures Choosing a ADC, How to read datasheets Practical Aspects, MCP3551 Applications Design, Applications & PCB Issues
Slide 2

Hands-on Material
MCP3551 USB PICtail Board MCP3551/3 Data Sheet Screwdriver PC + software (MXLAB IDE, DataView, scientific calculator) Your brain!
Slide 3

A/D Conversion Basics

What everybody should know!

Slide 4

Ideal A/D Converter

N-bits resolution ADC : Unipolar ADC: 1 LSB = Vref/2N Bipolar ADC: 1 LSB = Vref/2N-1 An Ideal ADC shows quantization error due to the nature of the digital output also called quantization noise although deterministic signal! - max = LSB, RMS =1/12 LSB - SNQRmax (dB) = 6.02N + 1.76 (for a sinewave input)
Slide 5

Real A/D Converter

Vref Vin+ VinGnd Vdd CS SDO SCK

Non-idealities and limitations due to CMOS Static Errors (Offset, Gain, INL, DNL) Dynamic Errors (Noise, Distortion, Drift) Other Circuit limitations (PSRR, CMRR, stability, dynamic range, bandwidth, aliasing, latency, clock jitter, aperture time) Digital Interface/Coding
Slide 6

MCP3551

Linear Static Errors

Static Errors that can be calibrated out (internally or externally with a MCU) by simple transformation Offset Error
Defined by the position of the zero Translation

Gain Error
Defined by the slope of the transfer function Rotation

Slide 7

Non-Linear Static Errors

Static Errors that cannot be calibrated out or at least not by simple transformations DNL Error
Transition Step Size DNL<1 LSB : No missing codes

INL Error
Deviation from an ideal straight line End Points Best Fit

Slide 8

Resolution vs. Accuracy

Resolution: Number of distinct output levels Accuracy: Difference between the ideal converter transfer function and the actual transfer function A 12-bit resolution ADC may be 10-bit accurate only! A 10-bit resolution ADC may have 12-bit accuracy!
A 3-bit resolution ADC perfectly accurate A 16-bit resolution ADC with 3-bit accuracy

Slide 9

The Sampling Theorem

When sampling a signal, the sampling frequency must be greater than twice the bandwidth of the input signal (Nyquist frequency) in order to be able to reconstruct the original signal from the sampled version

Time

Frequency

Slide 10

Dynamic Errors
Deterministic errors: depend only on the given input
conditions (aliasing, distortion, tones,) same conditions (noise, drift,) Noise: Random variation of the output code with time (thus with frequency!)

Non-deterministic errors: Imply randomness even with

Distortion: Spurs in the output frequency spectrum (harmonics)

Slide 11

High Resolution ADC Architectures

Focus on the - A/D Converter

Slide 12

ADC Architectures Overview

Delta-Sigma converters are mainly used for highresolution, low bandwidth applications There are two trends in the field towards higher bandwidth and higher resolution
Slide 13

SAR ADC Architecture

Very prevalent, used inside many MCUs Up to 16 bits resolution Medium speed, range from <10 kSPS to > 1 MSPS Easy to multiplex, one-shot converter Prices are relatively low Principal drawbacks: Anti-aliasing filter is often required at the input (Nyquist theorem). High resolution is expensive (mostly due to high-resolution DAC cost).
Slide 14

Dual Slope Architecture

Standard High performance ADC before Delta-Sigma High Resolution up to 18-bit in CMOS (5 digit DVMs) Small dependency on component tolerances Low output noise due to averaging High rejection of line frequencies Principal drawbacks: Low speed, External capacitors and resistors very often required
Slide 15

The Delta-Sigma Architecture

The modulator is an analog feedback loop which is sampling the input fast (oversampling); giving a very low resolution signal, estimator of the input signal This signal is very often a fast 1-bit signal called bitstream; containing quantization noise to be averaged out by the decimation filter to obtain a good representation of the input The decimation filter takes the bitstream out of the modulator and averages it to have a N-bit word out
Slide 16

Delta-Sigma Modulator
The modulator runs at the oversampling frequency fs V(z) = STF(z) U(z) + NTF(z) E(z) STF: Signal Transfer Function NTF: Noise Transfer Function The principle of the modulation is simple: obtain a simple digital estimator of the incoming signal and reprocess it in the loop filter in order to minimize the error E introduced by the rough quantization The STF gain needs to be close to unity in the desired bandwidth and the NTF gain close to zero to obtain good performance The system is non-linear due to the presence of the quantizer The quantizer can be a simple comparator of a Flash ADC The DAC can be either 1-bit (inherently linear) or multi-bit
Slide 17

Modulator Implementation Example

3rd order single-bit single-loop switched capacitors modulator using cascade of feedforward integrators Very linear: 1-bit DAC has inherent linearity Only first op amp is crucial (high gain, low offset) Front-end needs great care (circuit and layout)

DELTA

SIGMA

Slide 18

Oversampling and Noise Shaping

Magnitude

Digital Filter

STF NTF

SNQRmax vs OSR vs order (N)

f0

2f0 Nyquist

Oversampling

fS

frequency

Noise shaping: Quantization noise high pass filtering The modulator order is the number of integrators in the loop filter; it defines also the number of NTF zeros in the signal bandwidth thus the order of noise shaping Oversampling ratio (OSR): Ratio between oversampling frequency and Nyquist frequency; it is the decimation rate (Hz) of the digital filter The SNQR depends on modulator order and OSR
Slide 19

Digital Decimation Filter

The SINC or Comb filter is the most common used filter and the most simple to implement! It calculates a moving average of the incoming bit stream; the moving average acts as a windowing function For a L-th order modulator, a L+1-th order filter is recommended because of quantization noise filtering issues Main Notch frequency dependant on internal oscillator accuracy.
1 + z + z + ... + z D( z ) = OSR
1 2 1OSR

L +1

SINC filter transfer function

30

60

90

120

150

180 20 40 60 80 100 120

Rejection Magnitude [dB]

0 20 40 60 80 100 120 0 30 60 90 120 150 Input Frequency [Hz]

140 180

Slide 20

Digital Filter Implementation

Sigma Delta

Hogenauer structure, scalable and easy to implement Series of integrators (sigma) followed by a down-sample and by a series of differentiators (delta) Sigma operations are OSR times faster than delta ones Inputs can be 1-bit or multi-bit bitstreams Use of 2s complement arithmetics to avoid saturation Other transfer functions and structures exist based on the same philosophy
Slide 21

Benefits of Modulation
Very high Resolution: 20+ bits or <1V resolution Excellent Line Frequency and Noise Rejection High Linearity if 1-bit DAC is used Analog process requirements are minimized Anti-aliasing filter requirements are minimized Low Power Consumption: filtering is done in the digital section Applications: Wide Dynamic Range, Low Frequency Signals
Slide 22

Choosing a ADC
How to read and compare the datasheets

Slide 23

LSB, ppm, V,the units jungle

Datasheets are using different units for noise, INL, DNL, offset, gain error Try to compare datasheets with same units Try to convert all voltage related specs to same units 1 ppm = 1 part per million = 0.0001% Be careful, for quantities like INL, units like are often in ppm FSR or ppm of 2*Vref For a N-bit resolution bipolar converter: 1 LSB = Vref/2N-1 x 1000000 ppm FSR
Slide 24

Linearity: the weak point of

INL max is on the order of magnitude of 15 ppm FSR or 16-bit, for any ADC on the market Linear error compensations are easy but non-linear ones are tricky and not cost-effective Architecture inherently linear using 1-bit DAC structures but the input voltage is sampled on a capacitor A sigma-delta ADC using switched-cap circuit will be at best as linear as the input caps are; capacitors in CMOS processes are non-linear; they have a quadratic characteristic with respect to their voltage sampled across INL for a ADC is very often a function of Vref MCP3551: INL=12 ppm max with Vref=5V , INL=4 ppm max with Vref=2.5 V
Slide 25

Total Unadjusted Error

The Total Unadjusted Error is a common Figure of Merit (FOM) for static errors Combination of: Offset Error Gain Error Linearity Error Missing codes Characteristic of the ADC Mostly defined by process and calibration schemes Do not include VCM, power supply effects, beware of the conditions! TUE depends a lot on input voltage and Vref
Slide 26

Rejection Specifications
The line frequency rejection is proportional to the decimation filter order Common Mode DC and 50/60 Hz Rejection
How the part is sensitive to common-mode variation of the differential inputs; be careful to the conditions it is measured

Normal Mode 50/60 Hz Rejection

Decimation filter specification, typically huge at line frequency so that no line ripple can affect the output code

Power Supply DC Rejection

Important Analog design specification, high PSRR may give less constraints on power supply system design

Power Supply 50/60 Hz Rejection

Even higher than Normal mode rejection since PSRR of the analog modulator is already quite large
Slide 27

Digital Filter Latency

3rd order w/ latency Start convert Data Ready Data Ready Data Ready and accurate Time

3rd order no latency Start convert Data Ready and accurate Time

Latency: number of data ready to wait in order to have a valid and accurate output code The latency is caused by digital filter settling time which is typically proportional to OSR x order No latency designs (MCP3551) will have slower data rates but single cycle conversions: easy to multiplex; they wait for the data to be settled in order to give the data ready flag The real output data rate to consider is the one with latency especially when multiplexing
Slide 28

Noise Representations
Output noise is one of the critical specifications of a Delta-Sigma ADC As a non-certain signal, noise can be described with a statistical distribution giving a probability of output codes Noise units: In nV/Hz: spot noise taken over a 1Hz bandwidth In V RMS is the root mean square average of the output codes (Total noise integrated during conversion) Typical representation: noise histogram where the output code distribution is given for a certain number of conversions A noise histogram on every code transition would give a complete No missing code check
Output Code

Time nV/ Hz

Frequency

Slide 29

Noise Distribution
Occurrence Probabilty [%] 50 40 30 20 10 5 4 3 2 1 0 1 2 Output Code in 5 4 3 2 1 0 1 2 3 4 5

x 1 f (x) = exp 2 2 2
2

40 30 20 10 0 3 4 5

can be expressed in LSB, or V

Gaussian distribution is the most typical distribution for physical quantities like output noise Infinite spread but most of the probability is within the range which is the variance of the distribution: RMS noise Noise adds in squares! Averaging technique divides by n the noise level if n samples are used Commonly-used modeling for analyzing system noise: Superposition of uncorrelated noise sources
Slide 30

Reading Noise Histograms

Reading noise histograms can give precise idea of noise distribution at one point; noise distribution will vary with frequency and input conditions Peak-to-peak amplitudes are depending on low probability events (outside of the bell) thus hard to reproduce/evaluate The Crest Factor is the Ratio between Peak-to Peak signals and RMS signal; it is calculated here as a probability factor of occurring inside a certain range; industry generally uses a crest factor of 6.6 to specify peak-to-peak noise (99.9% event)
Distribution range
2.0 x RMS (1 sigma) 3.0 x RMS (1.5 sigma) 4.0 x RMS (2 sigma) 5.0 x RMS (2.5 sigma) 6.0 x RMS (3 sigma) 6.6 x RMS (3.3 sigma) 8.0 x RMS (4 sigma) 10.0 x RMS (5 sigma)

Probability of output codes in the range

68 % 87 % 95.4 % 98.8 % 99.73 % 99.90 % 99.954 % 99.994%

Probability of output codes not in the range

32 % 13 % 4.6 % 1.2 % 0.27 % 0.10 % 0.046% 0.006%

2
Average output code Average output code
Slide 31

Effective Number of Bits

ln ( FSR / RMS Noise) ENOB = ln (2)
Effective Number Of Bits (ENOB) or Effective Resolution is a figure of merit for the noise performance of the ADC The effective resolution gives the noise-free resolution of the device MCP3551: 2.5 VRMS noise 21.9 bits Effective Resolution (FSR=2*Vref=10V) You can optimize the Effective Resolution by using larger Vref because noise floor is almost constant with Vref (look for admissible Vref range)
Slide 32

Over-sampling and Noise

An Over-sampling ratio increase diminishes the output noise with the following schemes:
Doubling the OSR typically gives the SNR additional 6L dB or L bits per octave for one-shot ADCs Doubling the OSR divides by two the thermal noise power, -bit (1/2) thermal noise decrease per doubling of OSR

1/f noise becomes the limiting factor for very high OSRs

nV/ Hz

Frequency

Example of OSR table vs ENOB

Slide 33

Power Consumption Figure Of Merit

Power ADC Efficiency = ENOB 2 f OUT

The ADC efficiency is a figure of merit in order to compare different ADCs Power consumption It corresponds to the energy needed to achieve the effective resolution at a certain data rate; the units are in pJ/conversion MCP3551 is one of the leaders in ADC efficiency compared to similar ADCs MCP3551 ADC Efficiency = 11 pJ/conversion An efficient ADC has thermal noise and quantization noise on the same order of magnitude
Slide 34

Practical Aspects MCP3551 Applications

How to use MCP3551

Slide 35

Applications
Bridge sensing for pressure, strain, and force Temperature sensing with RTD, thermistor or thermocouple LM 4140 Weight scales Vref Vdd Gas analyzers Vin+ CS Bridge SPI Instrumentation VinSDO Sensor Interface Gnd SCK Data acquisition 6-digit DVMs Strain-gage transducers Industrial process control
MCP3551
Slide 36

Reduce Signal Conditioning Circuitry

Before

NOW

PIC MCU

Use High Resolution to your advantage: Remove unnecessary signal conditioning circuits!
Slide 37

Small Signal Applications Example

IR Temperature Sensor (Thermopile)

Think of the needed resolution in V not in bits!

Sensor Sensitivity: 29 to 55 V/C Medical Temperature Range: 34C to 42C 336V Input Voltage Range, 4.2V typ. for 0.1C resolution Need for high resolution A/D like MCP3551!
30K

20V/C 20V/C
30K

MCP3551 ADC

Thermopile Sensor
Slide 38

Ratiometric Use of VREF

Same principle than for CMOS analog IC design: base your design on ratios not on absolute values Powerful technique because any noise from VREF is theoretically cancelled out Ratio of input voltages is constant even if VREF is noisy No need to calibrate Still to consider accuracy and drift of the ratios of resistors (matching, heating)

VDD
LM 4140

VDD VREF VDD

IN+ IN-

GND MCP3551 AGND

Slide 39

MCP3551 Architecture
3rd order modulator with 1-bit DAC (OSR=512) Patented Autocalibration for offset and gain errors Modified 4th order Sinc filter for extended 50/60Hz rejection Low-tempco, low drift internal oscillator 3-wire SPI interface 8-pin MSOP package
Slide 40

MCP3551 Patented Calibrations

MCP3551 autocalibration for offset and gain errors is processed real-time (no delay, no internal disconnection of inputs) On-the-fly calibrations permit faster data rate and open the way to continuous operation without calibration phase

Offset Calibration: Fractal algorithm

Generalization of Chopper algorithm Principle: switch back and forth in a special way with adapted switch-cap circuit to cancel integrators offset

Gain Calibration: Rotating Caps

Dynamic Element Matching and scaling of the input caps Principle: DEM principle averages caps matching error and cancels gain error
Slide 41

MCP3551 Decimation Filter

4-th order modified Sinc filter with staggered zeros for wider notches Less constraints on notch centering MCP3551: >80dB rejection from 49 to 61 Hz. Reduce inventory cost for different markets (USA, Europe, Asia) MCP3550-50/60: >120dB rejection around chosen frequency (50 or 60 Hz 2%)
0 0 20 40 60 80 100 120 15 30 45 60 75 90 105 120 135 150 165 180 0 15 30 45 60 75 90 105 120 135 150 165 180

MCP3550-60

Input Normal Mode Rejection [dB]

0 20 40 60 80

20 40 60 80 100 120 140

MCP3551

20 40 60 80 100 120

100

15

30

45

60

75

90 105 120 135 150 165 180

15

Input Differential Signal Frequency [Hz]

30 45 60 75 90 105 120 135 150 165 180 Input Differential Signal Frequency [Hz]

Slide 42

Deal with Differential Inputs

Differential voltage inputs are very common for - ADC!
Vcm= ( Vin+ + Vin- ) / 2 Vdiff= Vin+ - Vin-

Beware of absolute voltages range and Vcm position to always be within specified range during operation
-Vref/2+Vcm<Vin<Vref/2+Vcm

If Vdiff is too large, an overload is detected (no code lock in MCP3551)

Slide 43

MCP3551 Operation
Initiating the Conversion
During shutdown, all internal circuits are off to give ultra-low IDDS spec A small start-up pipeline delay (<300us) is necessary to power-up at the beginning of the first conversion A small post-processing pipeline delay is needed to output the data (112 MCLK periods); after 1st conv, the delay between 2 data readys is tCONV

CS tCONV= 72.73ms Startup time <300us Shutdown MCLK (internal) f =112.64kHz 1st Conversion
2nd Conversion Data Ready

Filter 1st Order

Filter 2nd order

Filter 3rd order

Filter 4th order

X 512
1010010101110101010010010101010100101

22-bit word is ready here All filter registers are reset

Slide 44

MCP3551 Timings
SINC filter zeros located around 55Hz Rejection of 50 and 60 Hz Sampling Frequency at Input is 28.16 kHz (OSR = 512) Switching Frequency at Input is 112.64 kHz (4-phase system) Overall Data Rate at output is 13.75Hz
112.64kHz
Sample Input

112.64kHz
Transfer Charge

112.64kHz
Sample Reference

112.64kHz
Transfer Charge

28.16kHz
X 512
101001010001001

X 512
101001010001001

X 512
101001010001001

X 512
101001010001001

Filter Order 1 (55 Hz)

Filter Order 2 (55 Hz)

Filter Order 3 (55 Hz)

Filter Order 4 (55 Hz)

tCONV = 72.7ms (13.75Hz)

Slide 45

Is the Data Ready?

One-shot mode: SDO will either go HIGH or LOW on falling edge of CS to determine if the conversion has finished or not Continuous mode: SDO falling edge will indicate data ready

CS
Conversion Initiated Data Ready check on SDO Ready

tCONV

SDO
NOT Ready

SCK
Slide 46

Collecting the Data

SPI Communication
CS SCK
O V H O V L M S B B 2 0 B 1 9 B 1 8 B B 1 1 7 6 B 1 5 B 1 4 B 1 3 B 1 2 B 1 1 B 1 0 B B 0 0 9 8 B 0 7 B 0 6 B 0 5 B 0 4 B 0 3 B 0 2 B L 0 S 1 B

MCU data latched in

SPI Mode 1,1

CS SCK
D R O V H O V L M S B B 2 0 B 1 9 B B 1 1 8 7 B 1 6 B 1 5 B 1 4 B 1 3 B 1 2 B 1 1 B B 1 0 0 9 B 0 8 B 0 7 B 0 6 B 0 5 B 0 4 B 0 3 B B 0 0 2 1 L S B

SPI Mode 0,0

Reading data and converting can be done at the same time Data stays in memory until being read or updated (double buffered output)
Slide 47

Output Code Format

Analog Value OVH OVL 23 22 21 bit # Vref +1 LSB 1 0 bit2097153 1 Vref 1 0 bit2097152 1 Vref - 1 LSB 0 0 bit2097151 0 2 LSB 0 0 bit2 0 1 LSB 0 0 bit1 0 0 0 0 bit0 0 -1 LSB 0 0 bit-1 1 -2 LSB 0 0 bit-2 1 -Vref 0 0 bit-2097152 1 -Vref -1LSB 0 1 bit-2097153 0 20 0 0 1 0 0 0 1 1 0 1 19 0 0 1 0 0 0 1 1 0 1 18 0 0 1 0 0 0 1 1 0 1 17 0 0 1 0 0 0 1 1 0 1 Output Code 16 15 14 13 12 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 11 0 0 1 0 0 0 1 1 0 1 10 0 0 1 0 0 0 1 1 0 1 9 0 0 1 0 0 0 1 1 0 1 8 0 0 1 0 0 0 1 1 0 1 7 0 0 1 0 0 0 1 1 0 1 6 0 0 1 0 0 0 1 1 0 1 5 0 0 1 0 0 0 1 1 0 1 4 0 0 1 0 0 0 1 1 0 1 3 0 0 1 0 0 0 1 1 0 1 2 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Hexa B[23:0] 600001 600000 1FFFFF 000002 000001 000000 3FFFFF 3FFFFE 200000 9FFFFF

22-bit twos complement data coding OVH and OVL bits act as 23rd data bit up to 12% overrange; important for closed-loop operations OVH=OVL=1 indicates bad communication: can be used as an interrupt
Slide 48

Design, Applications & PCB Issues

A good ADC is nothing without a good system design

Slide 49

Switched-Cap Input Structure

Analog inputs are a switched capacitor stage where the sampling cap is charged and discharged A switched cap is acting like a resistor thus input current is proportional to voltage input MCP3551 input impedance about 2 M typical
VDD ILEAK IIN VIN RON Csample Analog Input structure

For absolute accuracy, you need to consider input R-C settling time here; input should settle to within 14 time constants of sample time for 1 ppm accuracy Example: MCP3551 switching frequency = 112640Hz; source impedance has to be chosen so that < 14/112640=634 ns
Slide 50

Decimation Filter Roll-off

Measuring AC signals, dont forget that the decimation filter is not ideal brick-wall The gain of the filter varies with frequency with the following magnitude plot (MCP3551):
0 15 30 45 60 75 90 105 120

Input Normal Mode Rejection [dB]

0
20 40 60 80 20 40 60 80 100 120 140

100
120

15

30 45 Input Differential

60 Signal

75 90 105 Frequency [Hz]

120

Slide 51

Anti-Aliasing Filter
For higher frequencies, greater than 120dB rejection at all frequencies except, around multiples of the oversampling rate Consider 1st order anti-aliasing filter design (Simple RC!) Locate R-C filtering close to MCP3551 analog input pins
0 28160 56320
0 0
- 20 - 20

84480

100000

Input Normal Mode Rejection [dB]

@ D

0
- 20 - 20

Input Normal Mode Rejection dB

20 40 60 80 100 120

Input Normal Mode Rejection dB

@ D

15

30

45

60

75

90

105

120

15

30

45

60

75

90

105

120

- 40 - 60 - 80 - 100 - 120

- 40 - 60 - 80 - 100 - 120

- 40 - 60 - 80 - 100 - 120

- 40 - 60 - 80 - 100 - 120

20 40 60

15

30 45 60 75 90 Input Differential Signal Frequency Hz

@ D
105

- 140

120

15

30 45 60 75 90 Input Differential Signal Frequency Hz

@ D
105

- 140

120

1*fs
Anti-Aliasing R-C filter

2*fs

3*fs

80 100 120 140

28160 56320 Differential Input Signal Frequency [Hz]

84480

100000

Slide 52

Building a Low-noise System

Evaluate your system requirements (resolution, noise floor, power consumption,) Choose the best architecture (make a noise budget for the system) Know your transducer/sensor characteristics (output range, noise, accuracy,) Evaluate/Calibrate static errors Evaluate and optimize the three types of Noise: Conducted Noise: Noise created by the propagation of signals inside the system Layout issues Radiated Noise: Noise created by the environment of the system (RF, EMI) Packaging/chassis issues Device Noise: Noise created by the electronic devices used in the system Devices issues
Slide 53

Voltage Reference Selection

Most important choice after ADC Low noise, low drift reference, calculate your error budget Beware of heating, look for low tempcos Low power is always appreciated in battery applications (think about total power budget) Choose a Vref value that matches your application (ex: low value for better linearity) Low output impedance is preferable
Slide 54

Voltage Reference Drift

Output codes with a poor reference:
~40ppm of Vref or 100V of drift (Vref = 2.5V)

Output codes with a stable reference:

~2ppm of Vref or 5V of drift (Vref = 2.5V)

Slide 55

Device Noise Overview

For Passive Devices, ideally only resistors generate noise: Resistors show thermal noise (equal to 4kT x R x BW) Ideal Inductors and Capacitors are noise-free, but real ones have small series resistances
nV/ Hz

1/f Noise Harmonic Distortion Broadband

Frequency

Active Devices: All types of integrated transistors (CMOS, BJT) have typically three different voltage noise sources 1/f Noise: due to random capture and release of charge carriers; inversely proportional to frequency of operation Thermal noise: Due to random thermal motion in resistive material; typically broadband and independent of DC current Shot Noise: Due to random diffusion and electron-hole pairs recombinations; typically broadband, proportional to DC current
Slide 56

Reducing Device Noise

GOLDEN Principle: Optimize the weakest link!
Dont forget that the noise adds in squares Choose lower value resistors Choose low series resistors capacitors and inductors Reduce the bandwidth of devices with filters Keep devices like op amps in linear operating range Use differential devices for op amps, ADCs Make clever device selection (low power, low noise) Optimize your CPU/MCU code to have less switching, less power consumed
Slide 57

Choosing Bypass Capacitors

Impedance ()
1M 100k 10k 1k 100 10 1 100 1f Tantulum 1k 10k 100k 1M 10M 1nf Ceramic 0.01f Ceramic

Frequency (Hz)
Bypass capacitors act as a charge reservoir for current spikes that are caused by fast edges; in order to have a good system PSRR, the bypass caps have to meet a low target impedance over the full frequency range Do not hesitate to put different caps in parallel covering different frequency ranges: Low MHz range: high capacitance, low ESR Tantalum Electrolytic - Small size, large values, medium inductance High MHz/GHz range: medium capacitance, low ESL Ceramic - Small size, low cost, good stability, low ESL, NPO, X7R
Slide 58

PCB Layout Strategies

Experiment different implementations for layout: Use the converter to validate your PCB layout experiments! System noise can be as low as 5V RMS even with a 2-layer board More layers are preferred for very quiet systems (testers, instrumentation) The key of layout is routing discipline Grounding is the first thing to consider The more symmetrical the better The simpler the better
Slide 59

PCB Layout Issues: GROUND

A low-noise, accurate system must have a stable, quiet reference point: GROUND! Provide current return path, wide power supply traces Separate Ground planes AGND and DGND but do not split them: star connection between AGND and DGND Good decoupling, for ex. 1uF tantalum w/ 0.1uF ceramic Grounding, grounding, grounding: ground plane under and around the MCP3551 (2" x 2" region) Minimize electric fields, magnetic fields, temperature gradients No CUTS or SLITS or SLOTS (these act as antennas)
Slide 60

PCB Layout: Analog Signals

Keep minimal length lines Thermo-coupling effects are huge in PCB vias If possible no Vias on VIN+, VIN-, VREF If vias, try to match them between VIN+, VIN-, VREF Minimize electric fields, magnetic fields, temperature gradients Isolate VIN+, VIN-, VREF lines from fast switching or full swing digital signals, split PCB Match VIN+, VIN- lines for minimal offset Interface directly with transducer
Slide 61

PCB Layout: Digital Signals

Digital signals do not only induce noise but also repetitive transient spikes that cause deterministic errors Isolate fast transients, full swing digital signals from the rest Fast edges on the edge! Digital circuits should have their own supply Since reading and converting can be done simultaneously, use series resistors (10k) on digital interface signals

Slide 62

System Design Example: Demonstration Board

Slide 63

Summary
You should know:
A/D Conversion Basics What are the High Resolution ADC Architectures How to Choose a ADC, How to read datasheets How to use MCP3551, what are the MCP3551 Applications How to build your low-noise high accuracy system/PCB Now Good Luck!
Slide 64