INTEGRATED CIRCUITS

DATA SHEET

TDA8425
Hi-fi stereo audio processor;
I2C-bus
Product specification
File under Integrated Circuits, IC02

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

GENERAL DESCRIPTION
The TDA8425 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel facility, digitally
controlled via the I2C-bus for application in hi-fi audio and television sound.
Feature:
Source and mode selector for two stereo channels
Pseudo stereo, spatial stereo, linear stereo and forced mono switch
Volume and balance control
Bass, treble and mute control
Power supply with power-on reset

QUICK REFERENCE DATA

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Supply voltage (pin 4)

VCC

10.8

12.0

13.2

Input signal handling

Vl

Vi

300

mV

(S+N)/N

86

dB

Total harmonic distortion

THD

0.05

Channel separation

80

dB

Volume control range

64

dB

Treble control range

12

12

dB

Bass control range

12

15

dB

Input sensitivity
full power at the output stage
Signal plus noise-to-noise ratio

PACKAGE OUTLINE
20-lead dual in-line; plastic (SOT146); SOT146-1; 1996 November 26.

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

Fig.1 Block diagram.

TDA8425

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

PINNING

Fig.2 Pinning diagram.

FUNCTIONAL DESCRIPTION
Source selector
The input to channel 1 (CH1) and channel 2 (CH2) is determined by the source selector. The selection is made from the
following AF input signals:
IN 1 L (pin 18); IN1 R (pin 20)
or
IN2 L (pin 1); IN2 R (pin 3)
Mode selector
The mode selector selects between stereo, sound A and sound B (in the event of bilingual transmission) for OUT R and
OUT L.
Volume control and balance
The volume control consists of two stages (left and right). In each part the gain can be adjusted between +6 dB and
64 dB in steps of 2 dB. An additional step allows an attenuation of 80 dB. Both parts can be controlled independently
over the whole range, which allows the balance to be varied by controlling the volume of left and right output channels.
Linear stereo, pseudo stereo, spatial stereo and forced mono mode(1)
It is possible to select four modes: linear stereo, pseudo stereo, spatial stereo or forced mono. The pseudo stereo mode
handles mono transmissions, the spatial stereo mode handles stereo transmissions and the forced mono can be used
in the event of stereo signals.

(1) During forced mono mode the pseudo stereo mode cannot be used.

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Bass control
The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in
steps of 3 dB.
Treble control
The treble control stage can be switched from +12 dB to 12 dB in steps of 3 dB.
Bias and power supply
The TDA8425 includes a bias and power supply stage, which generates a voltage of 0.5 VCC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to active, which mutes both parts of the treble amplifier. The muting
can be switched by transmission of the mute bit.
I2C-bus receiver and data handling
Bus specification
The TDA8425 is controlled via the 2-wire I2C-bus by a microcomputer.
The two wires (SDA serial data, SCL serial clock) carry information between the devices connected to the bus. Both
SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor.
When the bus is free both lines are HIGH.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in AC
CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition.
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition.
The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start
condition.
The bus is considered to be free again after a stop condition.
Module address
Data transmission to the TDA8425 starts with the module address MAD.

Fig.3 TDA8425 module address.

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Subaddress
After the module address byte a second byte is used to select the following functions:
Volume left, volume right, bass, treble and switch functions
The subaddress SAD is stored within the TDA8425. Table 1 defines the coding of the second byte after the module
address MAD.
Table 1

Second byte after module address MAD

128

64

32

16

MSB
function

LSB

volume left

volume right

bass

treble

switch functions

subaddress SAD
The automatic increment feature of the slave address enables a quick slave receiver initialization, within one
transmission, by the I2C-bus controller (see Fig.5).
Definition of 3rd byte
A third byte is used to transmit data to the TDA8425. Table 2 defines the coding of the third byte after module address
MAD and subaddress SAD.
Table 2

Third byte after module address MAD and subaddress SAD

MSB
function

LSB
6

volume left

VL

V05

V04

V03

V02

V01

V00

volume right

VR

V15

V14

V13

V12

V11

V10

bass

BA

BA3

BA2

BA1

BA0

treble

TR

TR3

TR2

TR1

TR0

switch functions

S1

MU

EFL

STL

ML1

ML0

IS

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Truth tables
Truth tables for the switch functions
Table 3

Source selector

function

ML1

ML0

IS

channel

stereo

stereo

sound A

sound B

sound A

sound B

Table 4

Pseudo stereo/spatial stereo/linear stereo/forced mono

choice

STL

EFL

spatial stereo

linear stereo

pseudo stereo

forced

mono(1)

Table 5

Mute
mute

MU

active; automatic
after POR(2)

not active

Notes
1. Pseudo stereo function is not possible in this mode.
2. Where: POR = Power-ON Reset.
Truth tables for the volume, bass and treble controls
Table 6

Volume control
2 dB/step
(dB)

V5

V4

V3

V2

V1

V0

62

64

80

80

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

Table 7

Bass control

3 dB/step
(dB)

BA3

BA2

BA2

BA0

15

15

12

12

12

Table 8

TDA8425

Treble control

3 dB/step
(dB)

TR3

TR2

TR2

TR0

12

12

12

12

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Sequence of data transmission

After a power-on reset all five functions have to be adjusted with five data transmissions. It is recommended that data
information for switch functions are transmitted last because all functions have to be adjusted when the muting is
switched off. The sequence of transmission of other data information is not critical.
The order of data transmission is shown in Figures 4 and 6. The number of data transmissions is unrestricted but before
each data byte the module address MAD and the correct subaddress SAD is required.

Fig.4 Data transmission after a power-on reset.

Fig.5 Data transmission after a power-on reset with auto increment.

Fig.6 Data transmission except after power-on reset.

October 1988

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Supply voltage

VCC

16

Voltage range for pins with external capacitors

Vcap

VCC

Voltage range for pins 11 and 12

VSDA, SCL

VCC

Voltage range at pins 1, 3, 9, 11, 12, 13, 18 and 20

VI/O

VCC

Output current at pins 9 and 13

IO

45

mA

Total power dissipation at Tamb < 70 C

Ptot

450

mW

Operating ambient temperature range

Tamb

70

Storage temperature range

Tstg

25

+150

Electrostatic handling, classification

A(1)

Note
1. Human body model: C = 100 pF, R = 1.5 k and V 4 kV;
charge device model: C = 200 pF, R = 0 and V 500 V.
DC CHARACTERISTICS
VCC = 12 V; Tamb = 25 C; unless otherwise specified
PARAMETER
Supply voltage

SYMBOL

MIN.

TYP.

MAX.

UNIT

VCC

10.8

12.0

13.2

ICC

26

35

mA

Vref

5.4

0.5 VCC

6.6

Vl

VREF

VO

VREF

Supply current
at VCC = 12 V
Internal reference voltage
Internal voltage
at pins 1, 3, 18 and 20
DC voltage internally generated;
capacitive coupling recommended
Internal voltage
at pins 9 and 13
SDA; SCL (pins 11 and 12)
input voltage HIGH

VIH

3.0

VCC

input voltage LOW

VIL

0.3

1.5

input current HIGH

IIH

+10

input current LOW

IIL

10

with external capacitors

pins 6 to 8, 14 to 17, 19,

Vcap.n

VREF

pin 2

Vcap.2

VCC0.3

Output voltage at pins

October 1988

10

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

AC CHARACTERISTICS (1)
VCC = 12 V; bass/treble in linear position; pseudo and spatial stereo off; RL > 10 k; CL < 1000 pF;
Tamb = 25 C; unless otherwise specified
PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

I2C bus timing (see Fig.7)

SDA, SCL (pin 11 and 12)
Clock frequency range

fSCL

100

kHz

The HIGH period of the clock

tHIGH

The LOW period of the clock

tLOW

4.7

SCL rise time

tr

SCL fall time

tf

0.3

Set-up time for start condition

tSU; STA

4.7

Hold time for start condition

tHD; STA

Set-up time for stop condition

tSU; STO

4.7

tBUF

4.7

tSU; DAT

250

ns

Vi(rms)

Ri

20

30

40

20

20 000

Hz

Time bus must be free before

a new transmission can start
Set-up time DATA
INPUTS
IN1 L (pin 18) IN1 R (pin 20);
IN2 L (pin 1) IN2 R (pin 3)
Input signal handling (RMS value)
at Vu = 12 dB; THD 0.5%
Input resistance
Frequency response (0,5 dB)
bass and treble in linear position;
stereo mode; effects off
OUTPUTS
OUT R (pin 9); OUT L (pin 13)
Output voltage range (rms value)
at THD 0.7%; Vi(max) 2 V

Vo(rms)

0.6

Load resistance

RL

10

Output impedance

ZO

100

gain = 6 dB

(S+N)/N

78

dB

gain = 0 dB

(S+N)/N

86

dB

gain = 20 dB

(S+N)/N

68

dB

cr

100

dB

Signal plus noise-to-noise ratio (weighted

according to CCIR 468-2); VO = 600 mV

Crosstalk between inputs at gain = 0 dB;

1 kHz; opposite inputs grounded (50 );
IN1L (pin 18) to IN2L (pin1) or
IN1R (pin 20) to IN2R (pin 3)

October 1988

11

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Total harmonic distortion

(f = 20 Hz to 12.5 kHz)
for Vi(rms) = 0.3 V;
gain = +6 dB to 40 dB

THD

0.05

for Vi(rms) = 0.6 V;

gain = 0 dB to 40 dB

THD

0.07

0.4

for Vi(rms) = 2.0 V;

gain = 12 dB to 40 dB

THD

0.1

cs

80

dB

RR100

50

dB

100

dB

maximum voltage gain (6 dB step)

Gmax

dB

minimum voltage gain (64 dB step)

Gmin

63

64

dB

mute position

Gmute

80

90

dB

dB

gain from 6 dB to 40 dB

Gstep

1.5

2.0

2.5

dB/step

gain from 42 dB to 64 dB

Gstep

1.0

2.0

3.0

dB/step

11

12

13

dB

11

12

13

dB

Resolution

Gstep

2.5

3.0

3.5

dB/step

October 1988

12

Channel separation at 10 kHz

gain = 0 dB
Ripple rejection (gain = 0 dB;
bass and treble in linear position)
fripple = 100 Hz
Crosstalk attenuation from logic
inputs to AF outputs (gain = 0 dB;
bass and treble in linear position)
VOLUME CONTROL
For truth table see Table 6
Control range at f = 1 kHz (36 steps)

Gain tracking error; balance in mid-position

Step resolution

TREBLE CONTROL
For truth table see Table 8
Control range
for C8-5; C14-5 = 5.6 nF
Maximum emphasis at 15 kHz with
respect to linear position
Maximum attenuation at 15 kHz with
respect to linear position

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

BASS CONTROL
For truth table see Table 7
Control range
for C6-7; C15-16 = 33 nF
Maximum emphasis at 40 Hz with
respect to linear position

14

15

16

dB

Maximum attenuation at 40 Hz with

respect to linear position
Resolution

11

12

13

dB

Gstep

2.5

3.0

3.5

dB/step

52

SPATIAL AND PSEUDO FUNCTION

Spatial:
Antiphase crosstalk
Pseudo:
Phase shift (see Fig.8)
Note to the AC characteristics
1. Balance is realized via software by different volume settings in both channels (left and right).

tSU; STA = start code set-up time.

tHD; STA = start code hold time.
tSU; STO = stop code set-up time.

tBUF = bus free time.

tSU; DAT = data set-up time.
tHD; DAT = data hold time.

Fig.7 Timing requirements for I2C-bus.

October 1988

13

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

curve

pin 17
(nF)

pin 19
(nF)

effect

15

15

normal

5.6

47

intensified

5.6

68

more intensified

Fig.8

Pseudo (phase in degrees) as a function of

frequency (left output).

Fig.9

Input signal handling capability; gain = 10 dB; RS = 600 ; RL = 10k; bass/treble = 0 dB; VCC = 12 V.

October 1988

14

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.10 Input signal handling capability plotted against gain setting; THD = 60 dB; f = 1 kHz; RS = 600 ;
RL = 10 k; bass/treble = 0 dB; VCC = 12 V.

Fig.11 Output signal handling capability; gain = 6 dB; RS = 600 ; RL = 10 k, bass/treble = 0 dB, VCC = 12 V.

October 1988

15

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.12 Source selector separation (channel 2 and channel 1); gain = 0 dB; Vi1 = 0 V; Vi2 = 1 V, RS = 0 ;
RL = 10 k; bass/treble = 0 dB; VCC = 12 V.

(1) gain = 0 dB; Vi = 1.0 V.

(2) gain = 6 dB; Vi = 0.5 V.

Fig.13 Stereo channel separation as a function of frequency; RS = 0 , RL = 10 k; bass/treble = 0 dB;

VCC = 12 V.

October 1988

16

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.14 Mute signal rejection as a function of frequency; gain = 0 dB; Vi = 1.0 V; RS = 0 ; RL = 10 k;

bass/treble = 0 dB; VCC = 12 V.

Fig.15 Ripple rejection as a function of frequency; voltage ripple = 0.3 V (rms); RS = 0 ; RL = 10 k;

bass/treble = 0 dB; VCC = 12 V.

October 1988

17

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.16 Noise output voltage as a function of gain; weighted CCIR468 quasi peak gain, + 6 dB to 64 dB;
Vi = 0 V, RS = 0 ; RL = 10 k; bass/treble = 0 dB; VCC = 12 V.

Fig.17 Frequency response of bass and treble control; bass and treble gain settings = 12 to +15 dB;
gain is 0 dB; Vi = 0.1 V; RS9 = 600 ; RL = 10 k; VCC = 12 V.

October 1988

18

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.18 Tone control with T-filter.

Fig.19 Tone control.

October 1988

19

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.20 Turn-on behaviour; C = 2.2 F; RL = 10 k.

Fig.21 Turn-off behaviour; without modulation.

Fig.22 Turn-off behaviour; with modulation

(shaded area).

October 1988

20

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

ICC = 25 mA
Iload = 239 mA
ton = 15 ms
toff = 110 ms

Fig.23 Turn-on/off power supply circuit diagram.

Fig.24 Level diagram.

October 1988

21

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

Fig.25 Test and application circuit diagram.

October 1988

22

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425

PACKAGE OUTLINE
DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

ME

seating plane

A2

A1

c
e

b1

w M
(e 1)

b
MH

11

20

pin 1 index
E

10

10 mm

scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT

A
max.

A1
min.

A2
max.

b1

mm

4.2

0.51

3.2

1.73
1.30

0.53
0.38

0.36
0.23

26.92
26.54

inches

0.17

0.020

0.13

0.068
0.051

0.021
0.015

0.014
0.009

1.060
1.045

e1

ME

MH

Z (1)
max.

6.40
6.22

2.54

7.62

3.60
3.05

8.25
7.80

10.0
8.3

0.254

2.0

0.25
0.24

0.10

0.30

0.14
0.12

0.32
0.31

0.39
0.33

0.01

0.078

(1)

(1)

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1

October 1988

REFERENCES
IEC

JEDEC

EIAJ
SC603

23

EUROPEAN
PROJECTION

ISSUE DATE
92-11-17
95-05-24

Philips Semiconductors

Product specification

Hi-fi stereo audio processor; I2C-bus

TDA8425
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in
our IC Package Databook (order code 9398 652 90011).

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 C, contact may be up to 5 seconds.

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260 C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

October 1988

24