TDA7339
3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
THREE STEREO INPUT
ONE RECORD OUTPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE- DIP28
RIAL I2 CBUS
DESCRIPTION
The TDA7339 is a volume and tone (bass , mid- ORDERING NUMBER: TDA7339
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I2C bus micro-
processor interface. Thanks to the used BIPOLAR/MOS Technology,
The AC signal setting is obtained by resistor net- Low Distortion, Low Noise and Low DC stepping
works and switches combined with operational are obtained.
amplifiers.
BLOCK DIAGRAM
R1 R3
2.7K 2.7K
C7 C9 C10 C13 C14
5.6nF 18nF 22nF 100nF 100nF
3x REC OUT(L) TREBLE(L) M IN(L) M OUT(L) B IN(L) B OUT(L)
2.2µF
2 8 3 6 7 9 10
C1
IN1(L)
C2 4 1st VOL 2nd VOL
IN2(L) 12
5 TREBLE MIDDLE BASS SOFTMUTE OUT L
C3
IN3(L)
MUTE 14
SCL
13
SDA
SERIAL BUS DECODE & LATCHES 18 BUS
MULTIPLEXER ADDR
27 15
C4 DIG.GND
IN1(R)
C5 25 1st VOL 11 CMUTE
IN2(R)
24 TREBLE MIDDLE BASS
C6 CSM 22nF
IN3(R) 2nd VOL
3x MUTE 17
SOFTMUTE OUT R
2.2µF
1
VS SUPPLY
16 28 21 26 23 22 20 19
ANAL.GND CREF REC OUT(R) TREBLE(R) M IN(R) M OUT(R) B IN(R) B OUT(R) D94AU067C
CREF C8 C11 C12 C15 C16
10µF 5.6nF 18nF 22nF 100nF 100nF
R2 R4
2.7K 5.6K
July 1999 1/12
This is preliminary information on a new product now in development. Details are subject to change without notice.
TDA7339
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VS Operating Supply Voltage 10.5 V
Tamb Operating Ambient Temperature -40 to 85 °C
Tstg Storage Temperature Range -55 to 150 °C
PIN CONNECTION
VS 1 28 CREF
IN1L 2 27 IN1R
TREBLE L 3 26 TREBLE R
IN2L 4 25 IN2R
IN3L 5 24 IN3R
M IN L 6 23 M IN R
M OUT L 7 22 M OUT R
REC OUT L 8 21 REC OUT R
B IN L 9 20 B IN R
B OUT L 10 19 B OUT R
CMUTE 11 18 ADDR
OUT L 12 17 OUT R
SDA 13 16 AGND
SCL 14 15 DIG GND
D95AU217A
THERMAL DATA
Symbol Parameter Value Unit
Rth j-amb Thermal Resistance Junction-pins 65 °C/W
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit
VS Supply Voltage 6 9 10 V
VCL Max. input signal handling 2 Vrms
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.08 %
S/N Signal to Noise Ratio 106 dB
SC Channel Separation f = 1KHz 100 dB
1st and 2nd Volume Control 1dB step -47 0 dB
Bass, Middle and Treble Control 1dB step -14 +14 dB
Mute Attenuation 100 dB
2/12
TDA7339
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb =
25°C Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUTS
R in Input Resistance 35 50 65 KΩ
1st VOLUME CONTROL
C RANGE Control Range 45 47 49 dB
AVMAX Maximum Attenuation 45 47 49 dB
Astep Step Resolution 0.5 1.0 1.5 dB
EA Attenuation Set Error G = 0 to -24dB -1.0 1.0 dB
G = -24 to -47dB -1.5 1.5 dB
Et Tracking Error G = 0 to -24dB 1 dB
G = 24 to -47dB 2 dB
Amute Mute Attenuation 80 100 dB
VDC DC Steps Adiacent Attenuation Steps 0 3 mV
From 0dB to AVMAX 0.5 5 mV
2nd VOLUME CONTROL
C RANGE Control Range 45 47 49 dB
AVMAX Maximum Attenuation 45 47 49 dB
Astep Step Resolution 0.5 1.0 1.5 dB
EA Attenuation Set Error G = 0 to -24dB -1.0 1.0 dB
G = -24 to -47dB -1.5 1.5 dB
Et Tracking Error G = 0 to -24dB 1 dB
G = 24 to -47dB 2 dB
AMUTE Mute Attenuation 80 100 dB
VDC DC Steps Adiacent Attenuation Steps 0 3 mV
From 0dB to AVMAX 0.5 5 mV
BASS
Rb Internal Feedback Resistance 32 44 56 KΩ
C RANGE Control Range ±11.5 ±14 ±16 dB
Astep Step Resolution 0.5 1 1.5 dB
MIDDLE
Rb Internal Feedback Resistance 18 25 32 KΩ
C RANGE Control Range ±11.5 ±14 ±16 dB
Astep Step Resolution 0.5 1 1.5 dB
TREBLE
C RANGE Control Range ±13 ±14 ±15 dB
Astep Step Resolution 0.5 1 1.5 dB
SUPPLY
VS Supply Voltage (note1) 6 9 10.5 V
IS Supply Current 4 7 10 mA
SVR Ripple Rejection 60 90 dB
SOFT MUTE
AMUTE Mute Attenuation 45 60 dB
tD Delay Time C SM = 22µF; 0 to 20dB; I = IMAX 0.8 1.5 2 ms
C SM = 22µF; 0 to 20dB; I = IMIN 15 25 45 ms
3/12
TDA7339
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUT
Vclip Clipping Level d = 0.3% 2 2.6 Vrms
R Ol Output Load Resistance 2 KΩ
RO Output Impedance 100 180 300 Ω
VDC DC Voltage Level 3.8 V
GENERAL
eNO Output Noise All Gains 0dB (B = 20 to 20kHz flat) 5 15 µV
Et Total Tracking Error AV = 0 to -24dB 0 1 dB
AV = -24 to -47dB 0 2 dB
S/N Signal to Noise Ratio All Gains = 0dB; VO = 1Vrms 106 dB
SC Channel Separation 80 100 dB
d Distortion AV = 0; V in = 1Vrms 0.01 0.08 %
BUS INPUTS
V il Input Low Voltage 1 V
Vih Input High Voltage 3 V
Iin Input Current Vin = 0.4V -5 5 µA
VO Output Voltage SDA IO = 1.6mA 0.4 0.8 V
Acknowledge
NOTE 1: the device is functionally good at Vs = 5V. A step down, on V S, to 4V does’t reset the device.
4/12
TDA7339
I2C BUS INTERFACE Acknowledge
Data transmission from microprocessor to the The master (µP) puts a resistive HIGH level on the
TDA7319 and viceversa takes place thru the 2 SDA line during the acknowledge clock pulse (see
wires I2C BUS interface, consisting of the two fig. 5). The peripheral (audioprocessor) that ac-
lines SDA and SCL (pull-up resistors to positive knowledges has to pull-down (LOW) the SDA line
supply voltage must be externally connected). during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
Data Validity The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
As shown in fig. 3, the data on the SDA line must tion of each byte, otherwise the SDA line remains
be stable during the high period of the clock. The at the HIGH level during the ninth clock pulse
HIGH and LOW state of the data line can only time. In this case the master transmitter can gen-
change when the clock signal on the SCL line is erate the STOP information in order to abort the
LOW. transfer.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to Transmission without Acknowledge
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran- Avoiding to detect the acknowledge of the audio-
sition of the SDA line while SCL is HIGH. processor, the µP can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
Byte Format sends the new data.
Every byte transferred to the SDA line must con- This approach of course is less protected from
tain 8 bits. Each byte must be followed by an ac- misworking and decreases the noise immunity.
knowledge bit. The MSB is transferred first.
Data Validity on the I 2CBUS
Timing Diagram of I2CBUS
Acknowledge on the I2CBUS
5/12
TDA7339
SOFTWARE SPECIFICATION address (the 8th bit of the byte must be 0). The
TDA7339 must always acknowledge at the end
Interface Protocol of each transmitted byte.
The interface protocol comprises: A sequence of data (N-bytes + acknowledge)
A start condition (s)
A stop condition (P)
A chip address byte, containing the TDA7339
TDA7339 ADDRESS
MSB first byte LSB MSB LSB MSB LSB
S 1 0 0 0 0 1 A 0 ACK DATA ACK DATA ACK P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION
Chip address
1 0 0 0 0 1 A 0
MSB LSB
A = Logic level ON pin ADDR
FUNCTION CODES
MSB F6 F5 F4 F3 F2 F1 LSB
1st VOLUME 0 F6 F5 F4 F3 F2 F1 0
2nd VOLUME 0 F6 F5 F4 F3 F2 F1 1
TREBLE 1 0 0 F4 F3 F2 F1 F0
MIDDLE 1 0 1 F4 F3 F2 F1 F0
BASS 1 1 0 F4 F3 F2 F1 F0
MUTMUX 1 1 1 F4 F3 F2 F1 F0
POWER ON RESET:
1st volume = 2nd volume = Mute
Treble = Middle = Bass = -14dB
Mutmux = Active Input IN 1
6/12
TDA7339
1st VOLUME CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
0 0 step 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 0 step 8dB
0 0 0 0dB
0 0 1 -8dB
0 1 0 -16dB
0 1 1 -24dB
1 0 0 -32dB
1 0 1 -40dB
1 1 1 MUTE
2nd VOLUME CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
0 1 step 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0 1 step 8dB
0 0 0 0dB
0 0 1 -8dB
0 1 0 -16dB
0 1 1 -24dB
1 0 0 -32dB
1 0 1 -40dB
1 1 1 MUTE
7/12
TDA7339
TREBLE CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 0 0 TREBLE BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB
0 1 0 0 1 9dB
0 1 0 1 0 10dB
0 1 0 1 1 11dB
0 1 1 0 0 12dB
0 1 1 0 1 13dB
0 1 1 1 0 14dB
0 1 1 1 1 14dB
1 0 0 TREBLE CUT
1 0 0 0 0 0dB
1 0 0 0 1 -1dB
1 0 0 1 0 -2dB
1 0 0 1 1 -3dB
1 0 1 0 0 -4dB
1 0 1 0 1 -5dB
1 0 1 1 0 -6dB
1 0 1 1 1 -7dB
1 1 0 0 0 -8dB
1 1 0 0 1 -9dB
1 1 0 1 0 -10dB
1 1 0 1 1 -11dB
1 1 1 0 0 -12dB
1 1 1 0 1 -13dB
1 1 1 1 0 -14dB
1 1 1 1 1 -14dB
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TDA7339
MIDDLE CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 0 1 MIDDLE BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB
0 1 0 0 1 9dB
0 1 0 1 0 10dB
0 1 0 1 1 11dB
0 1 1 0 0 12dB
0 1 1 0 1 13dB
0 1 1 1 0 14dB
0 1 1 1 1 14dB
1 0 1 MIDDLE CUT
1 0 0 0 0 0dB
1 0 0 0 1 -1dB
1 0 0 1 0 -2dB
1 0 0 1 1 -3dB
1 0 1 0 0 -4dB
1 0 1 0 1 -5dB
1 0 1 1 0 -6dB
1 0 1 1 1 -7dB
1 1 0 0 0 -8dB
1 1 0 0 1 -9dB
1 1 0 1 0 -10dB
1 1 0 1 1 -11dB
1 1 1 0 0 -12dB
1 1 1 0 1 -13dB
1 1 1 1 0 -14dB
1 1 1 1 1 -14dB
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TDA7339
BASS CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 1 0 BASS BOOST
0 0 0 0 0 0dB
0 0 0 0 1 1dB
0 0 0 1 0 2dB
0 0 0 1 1 3dB
0 0 1 0 0 4dB
0 0 1 0 1 5dB
0 0 1 1 0 6dB
0 0 1 1 1 7dB
0 1 0 0 0 8dB
0 1 0 0 1 9dB
0 1 0 1 0 10dB
0 1 0 1 1 11dB
0 1 1 0 0 12dB
0 1 1 0 1 13dB
0 1 1 1 0 14dB
0 1 1 1 1 14dB
1 1 0 BASS CUT
1 0 0 0 0 0dB
1 0 0 0 1 -1dB
1 0 0 1 0 -2dB
1 0 0 1 1 -3dB
1 0 1 0 0 -4dB
1 0 1 0 1 -5dB
1 0 1 1 0 -6dB
1 0 1 1 1 -7dB
1 1 0 0 0 -8dB
1 1 0 0 1 -9dB
1 1 0 1 0 -10dB
1 1 0 1 1 -11dB
1 1 1 0 0 -12dB
1 1 1 0 1 -13dB
1 1 1 1 0 -14dB
1 1 1 1 1 -14dB
MUTMUX CODES
MSB F6 F5 F4 F3 F2 F1 LSB FUNCTION
1 1 1 INPUTS
X X X 0 0 SLOW SOFT MUTE SLOPE (I=IMIN)
X X X 0 1 FAST SOFT MUTE SLOPE (I=IMAN)
X X X 1 X SOFT MUTE OFF
X 0 0 NOT ALLOWED
X 0 1 IN3
X 1 0 IN2
X 1 1 IN1
10/12
TDA7339
mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
a1 0.63 0.025
b 0.45 0.018
b1 0.23 0.31 0.009 0.012
b2 1.27 0.050
D 37.34 1.470
E 15.2 16.68 0.598 0.657
e 2.54 0.100
e3 33.02 1.300
F 14.1 0.555
I 4.445 0.175
DIP28
L 3.3 0.130
11/12
TDA7339
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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