IDDQ Testing Outline

! Introduction
! Inductive Fault Analysis
! Faults That Can Be Detected
! Circuit Constrains
! Design and Test Rules
! ATPG for IDDQ Testing
! Current Monitoring Methods
! Built-in Current Sensors
! QTAG Standard
! Deep Sub-micron Issues
! Some Specific Examples
! Conclusions
IDDQ testing.1

IDDQ Testing
IDD --- Current flow through VDD
Q --- Quiescent state
IDDQ Testing --- Detecting faults by monitoring IDDQ
VDD
IDD
Inputs

CMOS
circuit

Outputs

Normal IDDQ: ~10-9Amp.

Abnormal IDDQ: >10-5Amp.
IDDQ testing.2

Advantages of IDDQ Testing

"
"
"
"
"

Fault effect is easy to detect

Many realistic faults are detectable
ATPG is relatively simple
Test length is shorter
Built-in current sensing is possible

IDDQ testing.3

Inductive Fault Analysis (IFA)

A systematic method to generate realistic fault lists
Taking into account
Circuit fabrication technology
Defect statistics
Physical layout

IDDQ testing.4

Framwork of Inductive Fault Analysis

Technology
Description

Technology
Analysis

Primitive Fault
Taxonomy

Circuit
Layout

Layout
Parsing

Layout Data
Structures

Defect
Statistics

Defect
Generation

Defects

Primitive Fault
Extraction

Primitive
Fault List

Circuit Fault
Translation

Ranked Circuit
Fault List

IDDQ testing.5

Calculation of Defect Likelihood

Defect spot

Extra conductance

Missing insulator

Whether a fault presents depends on

1. Size of spot (defect statistics)
2. Distance of two conductors (layout)
3. Fabrication process
IDDQ testing.6

Defects in a Poly Path

(a) Defect-free poly path

(b) insignificant missing poly

(c) insignificant missing poly

(d) significant missing poly

IDDQ testing.7

Results of IFA

D efect Type
Fault
pin- m iss. extra m iss. extra m iss. extra m iss. extra m iss. all % of
C ategories holes m etal m etal poly. poly. diff. diff. p-w el p-w el cont. def. fault
l
l
s
B ridges
42
61
52
8
31
35
229 48%
B reaks
82
78
1
10
9
180 38%
C om bin.
1
1
0.2%
N ew T
2
.1
2
0.4%
T-S O N
62
62
13%
T-S O P
0.5
.05
0%
E xcept.
1
1
0.2%
(5,5,4)C ounter
D efect Type
Fault
pin- m iss. extra m iss. extra m iss. extra m iss. extra m iss. all % of
C ategories holes m etal m etal poly. poly. diff. diff. p-w el p-w el cont. def. fault
l
l
s
B ridges
111
257
125
12
62
78
645 48%
B reaks
281
230
4
21
29
565 42%
C om bin.
134
134 10%
N ew T
3
.3
0.2%
T-S O N
3
<1
3
0.2%
T-S O P
<1
<1
0%
E xcept.
2
2
0.2%
4 x 4 M ultiplier

Combin. : Both bridge and break present

T-SON(SOP): Transistor struck-on (stuck-open)
New T : New transistor created
IDDQ testing.8

New Transistors
diffusion

(A) Caused by extra poly

(B) Missing thinox

IDDQ testing.9

Faults That Can Be Detected

Bridge & stuck-on faults
Break faults
Line break
Gate break
Drain break
Source break
Transistor stuck-open faults
Other faults

IDDQ testing.10

Bridging & Stuck-on Faults

0 or 1?

0
logic
logic

0: 0V
1: 5V

2.5V
1

0 or 1?

Logic monitoring is inadequate !

IDDQ testing.11

Line Break Faults

5V

5V
Induce large
current

A floating node may drift to 1.5V~3.5V

and hence may turn on both PMOS
and NMOS transistors

IDDQ testing.12

Circuit Model to Analyze Break

Faults (Sheu TCAD-88)
Cgd0

Cdg
C1

Cgd
D
Cjd

C4

Cjs

Cgs
S

C3

Csg

C2

Csg0

Cgb

Cgb
S

S
IDDQ testing.13

Gate Break Faults

(Maly ICCAD 1988)

D
B

C1
d2

1. Off for VDS<Vth

2. Conducts a small Current for
Vth<VDS< .Vth
3. IDS (VGS-VDS) 2 for .vth<VDS
where = c1+c2 2
c2

C3
C4

In a gate

C2

large IDDQ

OV
Cgb
S
IDDQ testing.14

Source or Drain Break Faults

D
C1

B
d3
C3

C3

C4

C4

d1
C2

C2
Cgb

In a gate

C1

Cgb
May drift to
intermediate
voltage

IDDQ testing.15

Stuck-open Faults
A B C D O

A
B

T1 = 1 1 1 1 0

T2 = 0 0 0 1 ?
O

A
B
D

When T2 is applied, charge

sharing among x, y and o
occurs, hence may draw a
large current in the inverter.

IDDQ testing.16

Other Faults That Can Be Detected

Gate-oxide short (Hawkins ITC85, D&T 86)
Most stuck-at faults (Fritzmeyer ITC-90)
Latch-up
Delay faults
Any other fault due to extra conductor, missing
isolating layer, excess well/substrate leakage,
etc.

IDDQ testing.17

Circuit Constraints

To ensure IDDQ detectability, two conditions

must be satisfied:
1. Normal IDDQ must be small
2. Faults must result in large IDDQ

IDDQ testing.18

A Good Circuit That May Be Identified

As Being Faulty
A=011
B=110

x=11?
z=x0?

large
current

Sel=0 if AB=10

Output

1
MUX
0

When the third pattern AB=10 is applied, change sharing

between x, z occurs, and a large current may exist in the
inverter. However the output is still correct.

Problem due to high impedance node

IDDQ testing.19

A BF That Cannot Be Detected By IDDQ

a

=1: a=0, b=1

=1: Eventually x=y, no big current

Problem due to feedback loop

IDDQ testing.20

A BF That Is Masked By Another BF In a

Sequential Circuit








To detect (x,y)

A=0, B=1, W=0

To set W=0, z must be 0 during 1

If (x,z) exists, then z will become 1 during 1
IDDQ testing.21

A BF That Is Masked By Another BF In a

Combinational Circuit
x

A
w

B
z

O
C

To detect (x,y), we need A=0and z=0

So we have to set ABC=1x1 first and then ABC=010
If another fault (w,z) exists, then (x,y) cannot be detected
IDDQ testing.22

Problems with Dynamic Logic

x
Inputs

Problems: 1. Large current in normal circuits due to

charge sharing
2. Very few faults are detected because of the
precharge property
3. Fault masking of BF(a, b) due to BF(o, p)
IDDQ testing.23

Transistor Group
Output

G3

G2

Transistor group (TG) --"Channel-connected

component"

Connections between two

TGs are unidirectional

B
G1

C
E

Control direction or loop

can be defined

IDDQ testing.24

A Minimum Set of Design & Test Rule

for IDDQ Testing (Lee TCAD'92)
A1. Gate and drain (or source) nodes of a transistor are not in
the same TG.
A2. No conducting path exists from VDD to GND during steady
state.
A3. Each output of a TG is connected to VDD or GND during
steady state.
A4. No control loops among TGs exist.
A5. The bulk (or well) of an n-(p-)type transistor is connected
to GND (VDD).
A6. During testing, each PI is controlled by a monitored power
source.
IDDQ testing.25

Results of Design & Test Rules

Theorem 1: All irredundant single BFs in a circuit satisfying
A1-A6 can be detected using IDDQ testing.
Theorem 2: For a circuit satisfying A1-A6, a test detecting a
single BF f also detects all multiple BFs that
contain f.
Theorem 3: If any one of A1-A6 is removed, then circuits
exist for which IDDQ testing cannot give correct
test results.
Strategies for dealing with circuits not satisfying each rule
are required to ensure IDDQ detectability.

IDDQ testing.26

Fault Simulation
1. Fault models --- Bridging, break, stuck-open,
stuck-at ?
2. Fault list generation --- need inductive fault
analysis
3. Fault coverage ?
4. Easy for bridging and stuck-on faults
5. Difficult for break and stuck-open faults
6. Stuck-at faults may or may not be modeled as
short to VDD or GND

IDDQ testing.27

Fault simulation for BFs

If A1-A6 are satisfied, then fault simulation is
quite simple
1. Perform a good circuit simulation for the
given test pattern.
2. Any BF between a node with logic 1 and a
node with logic 0 is detected.
No simulation on faulty circuit is needed.
No fault list enumeration is needed.

IDDQ testing.28

Test Generation
1. Conventional test generation for stuck-at faults
can be modified to detect BFs.
2. No fault propagation.
3. Must make sure the faults result in a conducting
path between VDD and GND.
Switch level test generation may be necessary.
4. Break and stuck-open faults are difficult to detect.

IDDQ testing.29

Test generator for BFs

Again, assume A1-A6 are satisfied
1. For the BF (a, b) to be detected, add an XOR
gate with its inputs connected to a and b.
2. The test generator work is simply to set the
output of the XOR gate to be 1.

No Fault propagation.
IDDQ testing.30

Test Length Using IDDQ Testing for BFs

Prob. (a BF is detected by a random vector)
= 1/2
Prob. (a BF is not detected by n random
1 n
vectors) = ( )
2
If n=20,
1
Prob. (a fault is not detected) =
106
In general, the length of a complete test set
for BFs is quite small. Usually 30 is
enough for a combinational circuit.
IDDQ testing.31

Comparison Between IDDQ and Logic Testing

#faults

IDDQ Testing Fault Coverage(%)

Logic Testing

Circuit (reduced) 4 vec. 8 vec. 12 vec. 16 vec. 20 vec. time(s) #vec. FC

c432

263 97.65 99.62

99.96

c499

284 97.46 98.93

99.37

99.62

c1908

617 97.24 98.82

99.32

s386

350

93.1 96.78

s526
s832

Time(m)

4.04

50

79

11.4

99.73

9.15

184

87

30.5

99.59

99.75

21.4

138 84.8

28.6

98.00

98.74

99.07

7.51

288

75

28.6

1337 94.48 97.04

98.15

98.63

98.95

11.9

192 18.8

56.1

680 91.78 95.64

97.23

98.15

98.54

18.8

967 75.7

3.08

IDDQ testing.32

Test generation results for IDDQ test

(Source:1996 IDDQ Testing Workshop)
Total

Not Covered

Circuit Targets Tests Give-up

Untestable Time(s) Missing Rate(%)

c432

432

22

18

0.24

4.2

c499

546

82

0.57

c880

934

14

0.39

c1355

1482

83

5.4

0.2

c1908

1604

104

3.89

0.1

c2670

2253

23

17

4.59

1.2

c3540

3314

35

50

44.32

1.7

c5315

4955

24

6.13

0.1

c7552

6956

32

20

14.27

0.3

Average

2497

46

12

8.87

0.8
IDDQ testing.33

Current monitoring Techniques

ATE

ATE
Current Supply
Monitor

BICS

DUT

DUT

CUT

External
monitoring

Test
Fixture

Built-In
Current Sensor
IDDQ testing.34

External Devices (Hawkins 86, 89)

TEST POWER SUPPLY
RM

S (STROBE)

VDD
VDD pin

N
IDD

CN

DUT

Problems:

VSS pin

1. Current resolution is limitted.

2. Test equipment must be modified.
3. Current cannot be measured at the full speed of the tester.
4. Cannot partition circuit.
IDDQ testing.35

Built-in Current Sensors (BICSs)

VDD
VDD
Test

BICS

Pass
/Fail

Inputs

CUT

Outputs

OR
Inputs

CUT

Outputs

Test

BICS

Pass /Fail

Sometimes called ISSQ testing

IDDQ testing.36

BICS Based on Bipolar Transistor and Differential

Amplifier (Maly, ICCAD '88)
VDD
VDD

CMOS

Pass/Fail
Flag

Module
VR

1
1

VR

+ -

CMOS
Module
V

Virtual
Ground

Switching
circuit

GND

When large IDDQ exists, V>VR and Fail

flag is set.

VDD-GND Shorts

Shorts causing
struck-at faults
Shorts causing
bridging faults & oxide pinholes
Junction
leakages
NO defect

NO
defect

VR

The switching circuit may switch off a

faulty module to prevent large power
consumption

Defect

IDDQ testing.37

BICS Based on Logic Threshold

Favalli (JSSC-90)
VDD

VDD
Pullup

VDD

Pullup

inputs

Pullup

Normal : t = 1
Test
:t=0
tout = 1 if no fault
= 0 if fault exists

...
Pulldown

Pulldown

Pulldown
...

MT

MT

Gnd

MT
...

MTD
Gnd

tout
MTD

MTD
Gnd

IDDQ testing.38

Improvement on Favalli's design

VDD

Pullup

VDD

VDD

Pullup

inputs

Pullup
...

Pulldown

Pulldown

Pulldown
...
t

MT
tout

Merge all MT and MTD

respectively

MTD
Gnd
IDDQ testing.39

Improvement on Favalli's Design

VDD

Pullup

VDD

VDD

Pullup

inputs

Pullup
...

Pulldown

Pulldown

Pulldown
...
MT
tout

Using BiCMOS design

MTD
Gnd
IDDQ testing.40

BICS Based on Integrators

Miura & Kinoshita (ITC-92)
VDD

TVDD

MP7

CMOS
Logic
Circuit

MP1
MP3
MP8

MP2

X
V
MN1

MN2

MP4
MN4
MN3

Y
MP5
MN4

Tout
MN8

MP6
MN6

Tmode
MN7

I
NGND

V-I Translator

GND

Level Translator

Integral Circuitry

Fault effect can be accumulated through several clock cycles

IDDQ testing.41

Verhelst's BICS Patent

VDD'
CMS

SPC
Ts
T1

I2 A1 O1 M
+
IDD
I1

Io
CMP

VDD
Vref

In

CUT

O2

Iref

Vss

Virtual Short
Current Mirror

VDD' ~ VDD
IDD ~ I0
IDDQ testing.42

BICS Based on Dual Power Supply &

Operational Amplifier
VDD'=5V
RS

Virtual
Short

IRS

I+
I+

VoutIDD

VSS
Vin=3V

Vout+

VDD=3V

Threshold detector
CUT

Fault indication

Virtual short
VDD~Vin
Infinite input impedance of OP
I-=0 and IRS=IDD
IDDQ testing.43

BICS Based on Current Conveyor

Iz
Virtual
Short

V'DD=5V

Current Conveyor

Ix
VDD

Iy
Threshold
Detector
Fail/Pass

CUT

Virtual short
Current Conveying

VDD ~ VDD'
Iy ~ Ix
IDDQ testing.44

Advantages of Built-In Current Sensors

(BICS)
Higher test rate compared to external devices
Easier to partition circuits
Easier to control current resolution
Suitable for mixed-mode circuits
Built-In self test capability achievable
Lower test equipment cost
On-Line testing possible
IDDQ testing.45

Disadvantages of BICS
Impact on circuit performance
Reliability of itself
Area overhead
Power consumption

IDDQ testing.46

QTAG Standard
Motivation :
ATE based IDDQ facilities are not flexible or
effective.
Circuit designers are reluctant to use BICS.
Goal : To provide a de-facto standard for IDDQ monitors
on test fixture for production test.

IDDQ testing.47

Partnership of QTAG
Semicoductor test department:
Users, must drive the standard
ATE Vendors:
must supply the software to operate the
monitors from ATE
Test Fixture Vendors:
must provide a small area close to CUT on all
test fixtures to mount the monitors.
Monitor Developers:
must supply the desired monitors.
IDDQ testing.48

Development of the Standard

Kick-off meeting at ITC95, define 4 development
phases
--- phase 1: Monitor standard definition
--- phase 2: Monitor design
--- phase 3: Monitor evaluation
--- phase 4: Working toward a standard

Results are reported in 4 papers presented in ITC94

1994 OCIMU (off-chip measurement unit) was
developed by Alcatel
in 1995 ITC, the Monitor Description Format(MDF)
language is presented
POCIMU (threshold programmable)
1996 OCIMU
IDDQ testing.49

QTAG IDDQ Test Configuration

(Baker, ITC '94)

ATE

VDD MON

Vref

VDD PSU

Power Supply Unit

Ip
Bypass
Do
Di

IDDQ
MONITOR

VDD DUT

DUT

Vss
IDDQ testing.50

QTAG Monitor on a Probe Card

1
2
3
4

8
7
6
5

Power

QTAG Monitor
Power Ring

Control

Probe Nails

10 cm
IDDQ testing.51

An example of Interface to Digital ATE

VDD PSU

VDDmonitor

Power Supply Unit

1 2

3
Threshold
Pass-Fail
On-Off

6
4
8

MONITOR

ATE

Sample

VDDdevice

DUT

PIN
VDDdevice
VDDpsu
VDDmonitor
VSS
Pass/fail
Sample
ON-OFF

V
s
s

Threshold

Function
to device under test
to power supply
to secondary power source for monitor
group pin
Logic output indicate result of sample
High-level: under threshold when last sampled
Low-level: above threshold when last sampled
Positive clock edge to indicate sampling point
On is the monitoring mode
OFF stops monitoring, but gives low Ohms pat
VDDpsu to VDDdevice
Sets threshold limit for P/F as input voltage lev

IDDQ testing.52

Circuit Diagram of IDUNA-1

monitor
T7

T8
T11

T9

T10
VREF

T2

T1

T3

T5 T6

+
A2

VSS

VDM
Iout
CUT
IDDQ testing.53

Top-level Block Diagram of IDUNA II

DI TRIGGER

IREF

VDD_MON

KICK

VDD_PSU

12

BYPASS

VREF

Iref
Internal

Bypass

6
2

Output

Front

Back

10

DO

NC

11
100nF

VDD

VSS

Device under test

VSS

IDDQ testing.54

Front-end Circuit Diagram of IDUNA II

VDD_PSU

VREF

+
-

p2
p1

op_1

+
-

p3

op_2
IREF
NIA

NIB

NIC

VSS

VDD_DUT

iddq/2
IDDQ testing.55

Back-end Circuit Diagram

of IDUNA-2
VDDA
iref
P1

P2

P3
OP_3

aspass
iddq/2

N1

N7

N6

N2

N3

N8

+
-

N4
N5

VSS
IDDQ testing.56

Companies with Members in QTAG

AMD
AT&T
ATTEST
BNR
Bosch
Brooktree
Chips&Technologies
Cadence
Credence
CrossCheck
Digital

Ericson
GEC
HP
Intel
ITT
LIRM
LTX
MCT
Megatest
Motorola
National Semicon.

NEC
Philips
Sandia Lab.
Schlumberger
Sequent
Siemens
Sun
Synopsys
Teradyne
TI
Vertex
IDDQ testing.57

Deep Sub-micron IDDQ Test Issues

Components of Defect-free IDDQ
Reverse biased p-n junction leakage current
- State dependent reverse based p-n junction.
e.g., drain-substrate leakage
- State independent reverse biased wells.

Sub-threshold leakage
When VGS < VT, IDS =\ 0

IDDQ testing.58

Sub-Threshold Leakage Current

When VGS < VT, IDS is an exponential function
of (VGS-VT)
Define  =

    

 



Typically S=80

the inverse rate of decrease

of IDS in volts per decade






IDDQ testing.59

 In deep-submicron region,
low voltage power supply
low threshold voltage
increased subthreshold current
Example:

VT: 0.6 V 0.3 V

IDS increase by


  



=
  
 times
5600

IDDQ testing.60

Deep Sub-micron IDDQ test Options

Technology solution
Ex: Silicon On Insulator (SOI)

Technology solution

sharper sub-threshold
current slope

Ex:

Hierarchical power-line distribution with multiple

threshold transistors
Switched-Source impedcance (can reduce IDS to
0.3% of its original
value, very useful in
Giga-bit DRAM)
Technology solution

Ex: Separate Source and substrate connection

in the test mode
IDDQ testing.61

Applications and Examples

Low power design
Power management
Memory coupling test
CPU testing
Boundary scan + IDDQ Testing

IDDQ testing.62

Applications of IDDQ and IDDT Testings











!







!




 


!

IDDQ testing.63

IDDT-Testable SRAM Structure







VTCM

GTCM





V1

V2

V3

V4

V5

V6

V7

Vn-2

Vn-1

Vn



G1

 

G2
G3
G4
G5
G6



Gn-2
Gn-1
Gn



 



IDDQ testing.64

Some Experimental Results

(for a Dynamic Combinational logic)

Defect Coverages(%)

Total

Tested IDDQ IDDT IDDQ+IDDT Transition Test

Open drain/source

128

single floating gate

double floating gate
Short defects in the precharge chips

28.1 96.9

100

72.7

56

92.9

100

100

64.3

44

90.9

100

100

90.6

100

100

100

IDDQ testing.65

Conclusions

Extremely important to achieve high-quality test.

BICS can be either extremely profitable or nothing.
ATPG for faults other than BFs needs further research.
Deep sub-micron issues have to be addressed.

IDDQ testing.66