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Lab Assignment #4 Lab Assignment:: Name: Naresh Kumar Roll No: 2014-CE-180

Naresh Kumar is designing a 4-bit carry lookahead adder for lab assignment #4. A carry lookahead adder reduces computation time by generating carry signals in parallel using carry propagate (P) and carry generate (G) signals. The boolean expressions for P and G are defined, and the carry outputs for each stage are written in terms of P and G. Naresh provides the Verilog code for a full adder module and 4-bit carry lookahead adder module, along with a test fixture to generate test waveforms.

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Naresh Langhani
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85 views3 pages

Lab Assignment #4 Lab Assignment:: Name: Naresh Kumar Roll No: 2014-CE-180

Naresh Kumar is designing a 4-bit carry lookahead adder for lab assignment #4. A carry lookahead adder reduces computation time by generating carry signals in parallel using carry propagate (P) and carry generate (G) signals. The boolean expressions for P and G are defined, and the carry outputs for each stage are written in terms of P and G. Naresh provides the Verilog code for a full adder module and 4-bit carry lookahead adder module, along with a test fixture to generate test waveforms.

Uploaded by

Naresh Langhani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Name: Naresh Kumar

Roll no: 2014-CE-180

LAB ASSIGNMENT #4
Lab Assignment :
Design a 4 bit Carry Lookahead Adder.

THEORY
CARRY LOOKAHEAD ADDER
To reduce the computation time, there are faster ways to add two binary numbers by using carry
lookahead adders. They work by creating two signals P and G known to be Carry Propagator and
Carry Generator. The carry propagator is propagated to the next level whereas the carry generator is
used to generate the output carry,regardless of input carry.

Circuit Diagram
DESIGN ISSUES:
The corresponding boolean expressions are given here to construct a carry lookaheadadder. In the
carry-lookahead circuit we need to generate the two signals carry propagator(P) and carry
generator(G),
Carry PropagatorPi = Ai Bi
Carry GeneratorGi = Ai Bi

Having these we could design the circuit. We can now write the Boolean function for the carry
output of each stage and substitute for each Ci its value from the previous equations:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 P3 G2 P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

Name: Naresh Kumar

Roll no: 2014-CE-180

Verilog Module Code of FULL ADDER:

Verilog Module Code of 4 bit Carry LookaheadAdder :

Name: Naresh Kumar

Roll no: 2014-CE-180

Verilog Test Fixture Code

Waveform:

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