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Initial Begin // Initialize Inputs Clock 0 Clear 0

This document contains code for a counter module and testbench. The counter module uses a clock input and clear signal to increment a 4-bit register. The testbench initializes the inputs, applies pulses to the clear signal at specific times, and toggles the clock continuously to test the counter module.

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faizan khan
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35 views3 pages

Initial Begin // Initialize Inputs Clock 0 Clear 0

This document contains code for a counter module and testbench. The counter module uses a clock input and clear signal to increment a 4-bit register. The testbench initializes the inputs, applies pulses to the clear signal at specific times, and toggles the clock continuously to test the counter module.

Uploaded by

faizan khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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initial begin

// Initialize Inputs

clock = 0;

clear = 0;

// Wait 100 ns for global reset to finish

#10;

clear=1;

#20;

clear=0;

#280;

clear=1;

#10;

clear=0;

// Add stimulus here

end

always

begin

clock =~clock;

#20;

end

endmodule
module counter(

input clear,

input clock,

output reg[3:0] Q

);

always@ (posedge clear or negedge clock)

begin

if(clear)

Q<=4'd0;

else

Q<=Q+1;

end

endmodule

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