Digital Logic Design based

on Verilog HDL language

EE461 Lab

Verilog HDL Language 1

 What Is Verilog HDL Language ?
It is a hardware description language developed in
1984-1985 by Philip Moorby , who needed simple
way to describe digital circuits for modeling ,
simulation and analysis . The language become
the property of Gateway Design Automation .
Which was later acquired by Cadence Design
System . From 1990 , Cadence opened the
language to public.
Note :
The Syntax of Verilog HDL Language similar to
the C programming Language

Verilog HDL Language 2

 Field Programmable Gate Array (FPGA)
FPGA is a programmable
device that was first
introduced in 1985 by Xilinx
Co. consists of three main
parts as shown in Figure.
•A set of configurable logic
blocks.
•A programmable
interconnection network.
•A set of programmable
input and output cells around
the device.
3
Logic Array Blocks (LABs)
The logic blocks are arranged in a two-
dimensional array, depicted as hollow black
box; The interconnection wires, depicted as
solid blue box, are organized as horizontal
and vertical routing channels between rows
and columns of logic blocks. Programmable
connections also exist between I/O blocks
and the interconnection wires. FPGA can
implement circuit of more than a million
equivalent gates in size.

Logic Element (LEs)

Each logic array block (LAB) consists of 16
Logic Element (LEs). A LE is the smallest unit
of logic in the FPGA architecture. Each LE
has four inputs, a 4-input look-up-table
(LUT), a register, and output logic. The 4-
input LUT is a function generator that can
provide any function of four variables.
Verilog HDL Language 4
Lookup table (LUT) is the most
commonly used logic block in
FPGA.
A lookup table contains storage
cells that are used to implement a
small logic function.
Each cell is capable
of holding a single logic value,
either 0 or 1.
LUTs of various sizes may
be created, where the size
is defined by the number
of inputs.
LUTs are implemented
by using multiplexers.

Verilog HDL Language 5

Altera Cyclone III FPGA EP3C16

6
 General View of Typical CAD Flow for Design a Circuit

Verilog HDL Language 7

. Design Entry
The desired circuit is specified either by means of a schematic diagram, or by
using a hardware description language, such as Verilog or VHDL

• Synthesis
is the process of transforming a logic design specification into
an implementation. the entered design is synthesized into a circuit that
consists of the logic elements (LEs) provided in the FPGA chip
•
Functional Simulation
the synthesized circuit is tested to verify its functional correctness; this
simulation does not take into account any timing issues

• Fitting
The CAD Fitter tool determines the placement of the LEs defined in the
netlist into the LEs in an actual FPGA chip; it also chooses routing wires in the
chip to make the required connections between specific LEs
Verilog HDL Language 8
• Timing Analysis
Propagation delays along the various paths in the fitted circuit are
analyzed to provide an indication of the expected performance of the
circuit

• Timing Simulation
The fitted circuit is tested to verify both its functional correctness and timing

• Programming and Configuration

the designed circuit is implemented in a physical FPGA chip by programming the
configuration switches that configure the LEs and establish the required wiring
connections

Verilog HDL Language 9

 The System :
When the Verilog HDL Language using to describe
electronic system . Then the system is :
group of things or parts working together in a
regularAny system When
relation. need tothe
get input data from
electronic it’s
system is
environment
not very complex , and
it is output
usuallysome data
called in
a circuit.
return. ( Input / Output )
So , it’s the way to make the system
System : communicate with it’s environment.

Interface Body

Verilog HDL Language 10

 The System :
When the Verilog HDL Language using to describe
electronic system . Then the system is :
group of things or parts working together in a
The transformation
regular relation. When the electronicofsystem
data isand
not very compleximplementation
, it is usuallyofcalled
the desired function
a circuit.
is handled in Verilog by the system’s
Body , which is specified by the
System : module declaration.

Interface Body

Verilog HDL Language 11

 Modeling Structure :
 The module is the basic building block in
Verilog.
- Modules can be interconnected to describe the
structure of your digital system. The module
representing both system’s Interface and it’s
Body

- Modules start with keyword module and end with

keyword endmodule

Verilog HDL Language 12

 Modeling Structure :
- Syntax :
- module <module_name> ( <port_name > , <port_nme> , ….) ;
- <port_decleration> ;
- ‘ include “….”
- ………………………………….
- ………………………………….
- endmodule
Interface part
- Ex :
- module CPU (<port_name> , <port-name> , ..…) ;
- …………………………….
- ……………………………
- endmodule

Verilog HDL Language 13

 Modeling Structure :
- Syntax :
- module <module_name> ( <port_name > , <port_nme> , ….) ;
- <port_decleration>;
- ‘ include “….”
- ………………………………….
- ………………………………….
- endmodule

- Ex :
- module CPU (<port_name> , <port-name> , ..…) ;
- …………………………….
- …………………………… Body part
- endmodule

Verilog HDL Language 14

 Port Declaration :
 Syntax :

 Port_direction [port_size] port_name ;

 Port_direction :
 is declared as:
- input : for scalar or vector input ports.
- output : for scalar or vector output ports.
- inout : for scalar or vector bi_directional ports.

 Port_size : ( optional ) Is the range from [ msb : lsb ]

( most _significant_bit to least_significant_bit ).
The maximum port_size may be limited but will be at least
256 bits , and the default size is 1 bit.
Verilog HDL Language 15
 Port Declaration :
 We will describe this System :

A X_Gate B
Input ( 4 bits ) Output ( 1 bits )

 module X_Gate ( A , B ) ;
 input [ 3 : 0 ] A ;
 output B ;
 ……………..
 ……………..
 endmodule

Verilog HDL Language 16

 The Identifiers : ( Names )
 When you write any identifier like (module_name),
(port_name) , (block _name) …. etc , there are rules :

- Must begin with alphabetic or underscore characters a-z ,

A-Z , _ .
- May contain the characters a-z , A-Z , 0-9 , _ and $.
- Don’t use the keywords as identifiers.
- May use any character by escaping with a backslash ( \ )
at the beginning of the identifier , and terminating with a
white space.
- The Uppercase identifier is different than Lowercase
Identifier.

Verilog HDL Language 17

 The Identifiers : ( Names )

Examples Notes
adder Correct identifier name.
Beginning with a alphabetic.
xor Wrong identifier name.
Because (xor) is keyword.
1adder Wrong identifier name.
Because starting with a number
\reset* Correct identifier name.
Starting with (\) because it’s escapes identifier (
must be followed by white space )

Verilog HDL Language 18

 The Comment :
 There is no good design without proper documentation :
 Verilog allows two types of comments :

1) One_line comments: ( // …………. ).

start with two slashes ( // ) and terminate at the end of line.

2) Block_comments: ( /* ……………. */ ).
start with slash and asterisk ( /* ) and terminate with
asterisk followed by slash ( */ ). They can extend to
multiple lines.

• ( The types of Comment like C_programming Language. )

Verilog HDL Language 19

 The Comment :
 Example :

/* Description The X_Gate system

And all Input and Output ports for this System */

module X_Gate ( A , B ) ; // Module Declaration

input [ 3 : 0 ] A ; // Port Declaration

// A input (4_bits)

output B ; // Port Declaration for B (1_bit )

…………………………. /*
………………………….. The_Body */
endmodule

Verilog HDL Language 20

 Description Style :
 A Verilog circuit description can be one of two types :

 Structure Description :
Explains the physical makeup of the circuit , detailing gates and the
connection between them , ( Lower level components ) .

 Behavioral Description :
Is most advanced and most flexible. It’s also closest to programming
languages because uses sequential statements and allows compound
statement like conditional statement ( if ) , multiple choice ( case ) and
loops.Behavioral style describes a circuit in term of it’s behavior , and
behavioral style supports functions , ( always ) and ( initial ) blocks.
Behavioral Description also referred to an RTL ( Register
Transfer Level ) description.

Verilog HDL Language 21

 Structure Description :
 Structure Description dealing with Lower Level
Component :
1) Gates. 2) The connection between them ( Internal Signals ).

Gates Commands :
and , or , not , nand , nor , xor , xnor , buf

Internal Signals :
1) Nets : are physical connections between devices There
are many types of nets , but we use wire .

2) Register : Implicit storage – unless variable of this type is

modified it retains previously assigned value. Register type
denoted by reg .

Verilog HDL Language 22

 Structure Description :
X_Gate_System
 Example :

module X_GATE ( A , B , Y ) ;
input A , B ;
output Y ;

wire Y0 , Y1 ; // Y0,Y1 are interconnection between the and gates

and ( Y0 , A , B ) ;
and ( Y1 , A , B ) ;
or ( Y , Y0 , Y1 );
endmodule

Verilog HDL Language 23

 Continuous Assignment :
 If you want to drive a value onto a internal signals ( wire ,
reg ) , use a Continuous Assignment to specify an
expression for the wire or reg value.

 Syntax :

 assign <wire/reg_name> = <expression> ;

 Ex :
 module X_Gate ( A , B ) ;
 input A , B ;
 wire Y0 ; / / Y0 is internal signal ( Net_Type ).
 assign Y0 = A | B ; / / Continuous Assignment with wire_type
 endmodule
Verilog HDL Language 24
 Variable Declaration :
1) Declaration a Net ( wire ) :

wire [<range>] <net_name> , <net_name> …. ;

2) Declration a Register ( reg ) :

reg [<range>] <reg_name> , <reg_name> …. ;

Note :
Range is specified as [ msb : lsb ] . Default is one bit wide.

Verilog HDL Language 25

 Variable Declaration :
Examples :

reg r ; / / 1_bit reg variable.

wire w1 , w2 ; / / 2 wire variables each one is 1_bit.
reg [ 7 : 0 ] vreg ; / / 8_bit regesiter.
wire [ 7 : 0 ] w1 ; / / 8_bit wire variable.

Verilog HDL Language 26

 Logic Values :

The Verilog HDL has 4 logic values :

0: zero , logic low , false , ground.

1: one , logic high , true , power.
x or X : unknown.
z or Z : high impedance , unconnected , tri_state.

Verilog HDL Language 27

 Number specification :
Numbers are specified in the traditional form of
a series of digits with or without a sign but also in
the following form :

<size > <base_format> <number>

• <size> ( optional ) is the number of bits in the number.

Unsized integers default to the at least 32_bits.
• <base_format> ( optional ) is the single character ( ‘ )
followed by one of the following characters :

Verilog HDL Language 28

 Number specification :

Base Character
Binary b or B
Octal o or O
Decimal d or D
Hexadecimal h or H
Default <base_form> is Decimal.

• <number> contains digits which are legal for the <base_form>

Verilog HDL Language 29

 Number specification :
 Ex:

4 ‘ b11 / / 4_bit binary number 0011

5 ‘ d3 / / 5_bit decimal number
32 ‘ h00FF12EB / / 32_bit hexadecimal number
54 7834 / / Default : 32_bit decimal
number.

Verilog HDL Language 30

 Operators :
 Operators perform an operation on one or more
operands :

 1) Arithmetic Operators :

+ : Addition.
- : Subtract.
* : Multiply.
/ : Divide.
%: Modulus.

Verilog HDL Language 31

 Operators :
 2) Bitwise Operators :
 Bitwise operators operate on the bits of the two or more operands.
 For example : the result of ( A & B ) is the AND of each
corresponding bit of A with B.

~ : Bitwise Negation (NOT).

& : Bitwise AND.
| : Bitwise OR.
^ : Bitwise XOR.
~& : Bitwise NAND.
~| : Bitwise NOR.
~^ or ^~ : Bitwise XNOR.
Verilog HDL Language 32
 Operators :
 3) Relation Operators :
 Relation operators compare two operands and return a logic
value TRUE ( 1 ) or FALSE ( 0 ).

> : Greater than.

>= : Greater than or Equal.
< : Less than.
<= : Less than or Equal.
== : Logical Equality.
!= : Logical Inequal.

Verilog HDL Language 33

 Operators :
 4) Logical Operators :
 Logical operators operate on Logical operands and return a
logic value TRUE ( 1 ) or FALSE ( 0 ).

 Used typically in ( If ) and ( while ) statements.

! : Logical Negation.
&& : Logical AND.
|| : Logical OR.

Verilog HDL Language 34

 Operators :
 5) Shift Operators :
 Vacated bit positions are filled with Zeros.

<< : Shift Left ( Multiplication by power of 2 ).

>> : Shift Right ( Division by power of 2 ).

Verilog HDL Language 35

 Behavioral Description :
 Here in this type , you must describe the tasks and the
functions of this system , without structure details of
this system.
 In this type of description we use programming statement :
 1) IF_Else Conditional:
 The IF_Else Conditional execute a block of statements
according to the value of one or more expressions.
 IF_Else Conditional consists of keyword (if) followed by an
expression , if the value of this expression is true then
statement block that followed is executed . If the expression
value is false then the statement block after (else) is executed.

Verilog HDL Language 36

 IF_Else Conditional :
 Syntax : Ex :

 if ( <expression> ) if ( X == 1’ b1 )
 begin begin
 ……< statements > ....... Y=1‘ b0 ;
 end end

 else else
 begin begin
 ……< statements > ....... Y=X+1;
 end end

Verilog HDL Language 37

 The conditional statement if- else

if-else statements check a if (condition)

condition to decide whether statements;
or not to execute a portion if (condition)
statements;
of code. If a condition is
else
satisfied, the code is statements;
executed. Else, it runs this if (condition)
other portion of code. statements;
If it is necessary we can have else if (condition)
statements;
nested if else statements

Verilog HDL Language 38

Example
module math_op( i1,i2,a,x,y);
input i1 , i2 , a ;
output x , y ;
if (a == 1'b1)
begin
x =i1+i2;
y=i1*i2;
end
else
begin
x = i1-i2;
y = i1/i2;
end
endmodule

Verilog HDL Language 39

Example
module
mux_4_to_1(A0,A1,A2,A3,S0,S1,D);
input A0,A1,A2,A3,S0,S1;
output D;

If (S1 == 0 && S0 == 0)
D =A0;
else if (S1 == 0 && S0 == 1)
D = A1;
else if (S1 == 1 && S0 == 0)
D =A2;
else if (S1 == 1 && S0 == 1)
D =A3;
endmodule

Verilog HDL Language 40

 Behavioral Description :
 2 ) Case Statements:
 The Case Statement is similar in function to the ( IF_Else
Conditional ). The Case statement allows a multipath branch in
logic that based on the value of an expression.
 The Case Statements consists of keyword ( case ) followed by
expression followed by one ore more case items , the
expression is compared with each case item expression ,
One By One. When the expressions are equal , the condition
evaluates to true.
 Then the first case item that evaluates to true determines the
path , if no case item is true no action is taken , then in this
Case you can define a default case item.

Verilog HDL Language 41

 Case Statements :
 Syntax : Ex :
 case ( <expression> )
case ( X )
 case_item1 : begin
 ……<statements>……. 1’b1 : Y = X ;
 end
1’b0 : Y = X + 1 ;
 case_item2 : begin
 …….<statements>…….. default : Y = 1 ‘b0 ;
 end endcase
 default : begin
 ……..<statements>……… If (X_value) is not equal
 end (1‘b1) or (1‘b0) then (Y) will be
 endcase equal default case (1‘b0).

Verilog HDL Language 42

 The Case Statement

Case statement is used where there is one variable,

which needs to be checked for multiple values.
Any case statement should begin with case reserved
word, and end with endcase. It is better to have default
statement.
case (<expression>)
•Case statement supports single or <case1> : <statement>
multiple statements. <case2> : <statement>
•Group multiple statements using .....
begin and end keywords.
default : <statement>
endcase

Verilog HDL Language 43

 Example

module
mux_4_to_1(A0,A1,A2,A3,S0,S1,D);
input A0,A1,A2,A3,S0,S1;
output D;
case ({S1,S0})
00 : D = A0;
01 : D = A1;
10 : D = A2;
11 : D = A3;
default : D = A0;
endcase
endmodule

Verilog HDL Language 44

 Example

module
mux_4_to_1(A0,A1,A2,A3,S,D);
input A0,A1,A2,A3;
Input [1:0]S;
output D;
case (S)
0 : D = A0;
1 : D = A1;
2 : D = A2;
3 : D = A3;
default : D = A0;
endcase
endmodule

Verilog HDL Language 45

 Casez and Casex either the x or the z as don't
care instead of as logic values.
casez (G)
4'b1zzz : out = a ; // don't care about lower 3 bits
4'b01??: out = b ; //the ? is same as z in a number
4'b001?: out = c ;
default : out = $display ("Error xxxx does matches 0000");
endcase

Verilog HDL Language 46

 Variable Assignment

In the digital systems there are two types of

elements, combinational and sequential.
 Combination elements can be modeled using
assign and always statements.
 Sequential elements can be modeled using
only always statement.
 initial statement are used only in test benches.

Verilog HDL Language 47

 Behavioral Blocks :
 Initial and Always Blocks :
 There are two behavioral blocks ( Initial and Always block )
behave identical except for one thing :

 Initial Block : The contents of an Initial block is executed at the

very beginning of the simulation when ( time 0 ) and only once ,
the initial block never executes again.

 Always Block : An Always block also start at ( time 0 ) but it

contents is executed in an infinite loop and repeats for as long
as the simulation performed.

Verilog HDL Language 48

 Behavioral Blocks :
 Initial Block : Always Block :

initial always @ ( <Event_exp>)

begin begin
……….. ……………..
……….. …………….
……….. ……………
end end

Executed just Executed many

one time times

Verilog HDL Language 49

 Procedural Blocks
Verilog behavioral codes is inside procedures blocks,
but there is an exception, some behavioral code also
exist outside procedures blocks.
If a procedure block contains more then one statement,
those statements must be enclosed within:
 Sequential begin - end block
 Parallel fork - join block
Initial Initial
begin fork
#1 A = 0; #1 A = 0;
#3 B = 0; #3 B = 0;
#5 C = 0; #5 C = 0;
end join

Verilog HDL Language 50

 Procedural Blocks
Verilog behavioral codes is inside procedures blocks,
but there is an exception, some behavioral code also
A gets
exist0 after 1 timeprocedures
outside unit, blocks.
B gets 0 after 4 time units.
C If a procedure
gets block contains more then one statement,
0 after 9 time units.
those statements must be enclosed within:
All the statements are executed
in Sequential
sequentially. begin - end block
 Parallel fork - join block

Initial Initial
begin fork
#1 A = 0; #1 A = 0;
#3 B = 0; #3 B = 0;
#5 C = 0; #5 C = 0;
end join

Verilog HDL Language 51

 Procedural Blocks
Verilog behavioral codes is inside procedures blocks,
but there is an exception, some behavioral code also
A gets
exist0 after 1 timeprocedures
outside unit, A gets 0 after 1 time unit,
blocks.
B gets 0 after 4 time units. B gets 0 after 3 time units.
C If a procedure
gets block contains more
0 after 9 time units. C getsthen one
0 after statement,
5 time units.
those statements must be enclosed within:
All the statements are executed All the statements are executed
in Sequential
sequentially. begin - end block in parallel.
 Parallel fork - join block

Initial Initial
begin fork
#1 A = 0; #1 A = 0;
#3 B = 0; #3 B = 0;
#5 C = 0; #5 C = 0;
end join

Verilog HDL Language 52

 Initial statements

The Initial block provides initial values for

simulation purposes and does not play a
role in circuit synthesis.
The initial block, is used in conjunction
with a simulator to establish initial values.in
other words it excudes once at time zero.

Verilog HDL Language 53

 Example
module t_addr;
reg a,b,clk;
wire [0:1]c;
addr mmm (.a(a) , .b(b), .clk(clk), .c(c ));
always
#50 clk =~clk;
initial
begin
clk=0;
a =1;
b =0;
# 100 a=0;
# 150 b=1;
# 300 a=1;
# 200 b=0;
end
endmodule
Verilog HDL Language 54
 Always statements
The always statements loop to execute over and over again,
always have sensitive list or delay associated with it.
always @ ( sensitivity_list )
begin
<statement1>
<statement2>
………
end

The sensitivity list is a list of the variables which, if changed,

would produce a different output in the always block.

always statement can not drive a wire data type, but can
drive reg and integer data type
Verilog HDL Language 55
 Examples module dec_2to4(a,e,f);
input [1:0] a ;
Input e ;
module dec_2to4( a,f ); output [3:0] f ;
input [1:0] a ; reg [3:0] f ;
output [3:0] f ; always @ ( a or e )
reg [3:0] f ; begin
If (e==1) begin
always @ ( a ) case(a)
begin 2'b00: f=4'b0001;
case ( a ) 2'b01: f=4'b0010;
2'b00: f=4'b0001; 2'b10: f=4'b0100;
2'b01: f=4'b0010; 2'b11: f=4'b1000;
2'b10: f=4'b0100; endcase
2'b11: f=4'b1000; else
endcase f =4’b1111;
end end
endmodule end
endmodule
Verilog HDL Language 56
 Example

module addr (a,b,clk,c);

input a,b,clk;
output [0:1]c;
reg [0:1]c;

always @ ( posedge clk )

c = a+b;

endmodule

Verilog HDL Language 57

 Example always block could be
without sensitive list, in this
case we need to have delay

module addr (a,b,clk,c) ;

input a , b , clk ;
output [0:1] c; always
reg [0:1] c ; begin
#10 clk = ~clk ;
always @ ( posedge clk ) end
c = a+b;

endmodule

Verilog HDL Language 58

 Assign Statement

The assign statement executes continuously, it is

called continuous assignment statement as there is no
sensitive list.

assign statement can be used for modeling only

combinational logic

Verilog HDL Language 59

 Example

module tri_buf (A , B, ENB) ;

input A , ENB ;
output B ;
wire B ;
assign B = (ENB) ? A : 1'bz ;

endmodule

Verilog HDL Language 60

 Example
module dec_2to4 (a , f) ;
input [1:0] a ;
output [3:0] f ;
[3:0] f ;
assign
f = (a == 2'b00 ) ? 4'b0001 :
(a == 3'b01 ) ? 4'b0010 :
(a == 3'b10 ) ? 4'b0100 :
(a == 3'b11 ) ? 4'b1000 : 4’b1111 ;
endmodule

Verilog HDL Language 61

 Notes :
 All the keywords of Verilog HDL Language are lowercase.
 Most of Verilog’s instructions ended with ( ; ).
 When you write any description code ( instructions ) for any
system , you must know the structure or the behavioral of this
system.

THE END

Verilog HDL Language 62