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Commits on Dec 6, 2018

• Merge pull request #128 from sharebrained/external_clock_tweaks

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• Clock Manager: Large re-working to support external references.

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• bootstrap: Remove, not necessary.

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• Little code clarity improvement.

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• Pins: Miscellaneous SCU configuration tweaks.

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• Merge M0 and M4 to eliminate need for bootstrap firmware

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• PAL/board: New IO initialization code

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Commits on Dec 5, 2018

• PAL: Add functions to address The Glitch.

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• SCU: Add struct to hold pin configuration.

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• HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

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• GPIO: Tweak masking of SCU function.

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• clock generator: Use recommended PLL reset register value.

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• LPC43xx: Add MCPWM peripheral struct.

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Commits on Dec 4, 2018

• chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

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• Add LPC43xx functions.

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• Remove unused board files.

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Commits on Sep 29, 2018

• Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

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Commits on Sep 28, 2018

• Pin configuration: Disable input buffers on pins that are never read.

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• Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

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Commits on Sep 18, 2018

• PortaPack IO: Expose method to set reference oscillator enable pin.

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Commits on Sep 17, 2018

• ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

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• Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.

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• Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

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• Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

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• Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

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Commits on Sep 15, 2018

• Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

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• Bootstrap: Get CPU operating at max frequency as soon as possible.

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• Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

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• Clock Manager: Remove redundant clock generator output enable.

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• Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

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• Clock Manager: Use shared MCU CLKIN clock control configuration constant.

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• Clock Generator: Add a couple more setter methods for ClockControl registers.

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Commits on Sep 14, 2018

• CPLD: Bitstream to support new hardware features.

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• CPLD: Add pins and logic for new PortaPack hardware feature(s).

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• PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

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