Repositories list

• verilator

  Public

  chipsalliance/verilator’s past year of commit activity
  Verilator open-source SystemVerilog simulator and lint system

  C++

  •

  GNU Lesser General Public License v3.0

  •715•41•0•0•Updated Nov 13, 2025Nov 13, 2025

• caliptra-sw

  Public

  chipsalliance/caliptra-sw’s past year of commit activity
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

  Rust

  •

  Apache License 2.0

  •72•127•199•78•Updated Nov 13, 2025Nov 13, 2025

• chips-alliance-website

  Public

  chipsalliance/chips-alliance-website’s past year of commit activity
  SCSS

  •

  MIT License

  •7•4•8•9•Updated Nov 13, 2025Nov 13, 2025

• sv-tests-results

  Public

  chipsalliance/sv-tests-results’s past year of commit activity
  Output of the sv-tests runs.

  HTML

  •6•7•0•0•Updated Nov 13, 2025Nov 13, 2025

• t1

  Public
  Scala

  •

  Apache License 2.0

  •41•300•18•26•Updated Nov 13, 2025Nov 13, 2025

• caliptra-rtl

  Public

  chipsalliance/caliptra-rtl’s past year of commit activity
  HW Design Collateral for Caliptra RoT IP

  SystemVerilog

  •

  Apache License 2.0

  •66•116•85•18•Updated Nov 13, 2025Nov 13, 2025

• sv-tests

  Public

  chipsalliance/sv-tests’s past year of commit activity
  Test suite designed to check compliance with the SystemVerilog standard.

  rtlverilogsystemverilog+ 3hdlcompliance-testingsymbiflow

  SystemVerilog

  •

  ISC License

  •84•347•46•23•Updated Nov 13, 2025Nov 13, 2025

• adams-bridge

  Public

  chipsalliance/adams-bridge’s past year of commit activity
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)

  cryptographydigital-signaturelattice+ 2pqcml-dsa-87

  SystemVerilog

  •

  Apache License 2.0

  •8•39•14•1•Updated Nov 13, 2025Nov 13, 2025

• i3c-core

  Public

  chipsalliance/i3c-core’s past year of commit activity
  SystemVerilog

  •

  Apache License 2.0

  •13•37•17•3•Updated Nov 13, 2025Nov 13, 2025

• caliptra-mcu-sw

  Public

  chipsalliance/caliptra-mcu-sw’s past year of commit activity
  Caliptra MCU Software

  Rust

  •

  Apache License 2.0

  •23•21•87•12•Updated Nov 13, 2025Nov 13, 2025

• caliptra-ss

  Public

  chipsalliance/caliptra-ss’s past year of commit activity
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

  securityrotocp+ 3root-of-trustcaliptraopencomputeproject

  SystemVerilog

  •

  Apache License 2.0

  •31•32•75•17•Updated Nov 13, 2025Nov 13, 2025

• chisel

  Public

  chipsalliance/chisel’s past year of commit activity
  Chisel: A Modern Hardware Design Language

  scalachip-generatorchisel+ 4rtlchisel3firrtlverilog

  Scala

  •

  Apache License 2.0

  •640•4.5k•342•146•Updated Nov 12, 2025Nov 12, 2025

• Caliptra

  Public

  chipsalliance/Caliptra’s past year of commit activity
  Caliptra IP and firmware for integrated Root of Trust block

  Apache License 2.0

  •53•347•53•7•Updated Nov 12, 2025Nov 12, 2025

• riscv-vector-tests

  Public

  chipsalliance/riscv-vector-tests’s past year of commit activity
  Unit tests generator for RVV 1.0

  generatorspikeriscv+ 2testsuitervv

  Go

  •

  Apache License 2.0

  •31•95•10•1•Updated Nov 11, 2025Nov 11, 2025

• uvm-verilator

  Public
  SystemVerilog

  •

  Apache License 2.0

  •22•106•1•0•Updated Nov 11, 2025Nov 11, 2025

• Cores-VeeR-EL2

  Public

  chipsalliance/Cores-VeeR-EL2’s past year of commit activity
  VeeR EL2 Core

  fpgaprocessorriscv+ 11rtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digital+ 4

  SystemVerilog

  •

  Apache License 2.0

  •91•303•33•5•Updated Nov 10, 2025Nov 10, 2025

• caliptra-ureg

  Public

  chipsalliance/caliptra-ureg’s past year of commit activity
  Rust

  •

  Apache License 2.0

  •6•7•0•1•Updated Nov 7, 2025Nov 7, 2025

• caliptra-dpe

  Public

  chipsalliance/caliptra-dpe’s past year of commit activity
  High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

  Rust

  •

  Apache License 2.0

  •27•20•21•12•Updated Nov 7, 2025Nov 7, 2025

• firrtl-spec

  Public

  chipsalliance/firrtl-spec’s past year of commit activity
  The specification for the FIRRTL language

  TeX

  •31•62•25•17•Updated Nov 2, 2025Nov 2, 2025

• caliptra-web

  Public

  chipsalliance/caliptra-web’s past year of commit activity
  Astro

  •

  Apache License 2.0

  •1•0•0•0•Updated Oct 31, 2025Oct 31, 2025

• tac

  Public

  chipsalliance/tac’s past year of commit activity
  CHIPS Alliance Technical Advisory Council

  Apache License 2.0

  •27•7•18•3•Updated Oct 8, 2025Oct 8, 2025

• riscv-dv

  Public

  chipsalliance/riscv-dv’s past year of commit activity
  Random instruction generator for RISC-V processor verification

  Python

  •

  Apache License 2.0

  •359•1.2k•129•20•Updated Oct 1, 2025Oct 1, 2025

• chisel-template

  Public template

  chipsalliance/chisel-template’s past year of commit activity
  A template project for beginning new Chisel work

  Shell

  •

  The Unlicense

  •194•670•13•2•Updated Sep 22, 2025Sep 22, 2025

• verible-actions-common

  Public

  chipsalliance/verible-actions-common’s past year of commit activity
  Apache License 2.0

  •8•2•0•0•Updated Sep 17, 2025Sep 17, 2025

• caliptra-infra

  Public

  chipsalliance/caliptra-infra’s past year of commit activity
  Various tools used for Caliptra's Continuous Integration flows

  Rust

  •

  Apache License 2.0

  •1•0•0•1•Updated Sep 16, 2025Sep 16, 2025

• .github

  Public

  chipsalliance/.github’s past year of commit activity
  Organization profile for CHIPS Alliance

  2•0•2•0•Updated Sep 16, 2025Sep 16, 2025

• Surelog

  Public

  chipsalliance/Surelog’s past year of commit activity
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  parserlinterpreprocessor+ 11antlrverilogpython-apisystemveriloguvmelaborationvpi+ 4

  C++

  •

  Apache License 2.0

  •77•425•47•0•Updated Sep 6, 2025Sep 6, 2025

• UHDM

  Public

  chipsalliance/UHDM’s past year of commit activity
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  serializationlistenersystemverilog+ 3ieee-standardvpi-apivpi-interface

  C++

  •

  Apache License 2.0

  •43•237•14•0•Updated Sep 6, 2025Sep 6, 2025

• rocket-chip

  Public

  chipsalliance/rocket-chip’s past year of commit activity
  Rocket Chip Generator

  scalarocket-chipchip-generator+ 3chiselriscvrtl

  Scala

  •

  Other

  •1.2k•3.6k•252•69•Updated Sep 2, 2025Sep 2, 2025

• rvdecoderdb

  Public

  chipsalliance/rvdecoderdb’s past year of commit activity
  The Scala parser to parse riscv/riscv-opcodes generate

  Nix

  •11•21•1•1•Updated Sep 2, 2025Sep 2, 2025