Fix configured_value_or handling of bools.

Fixes #3923

PiperOrigin-RevId: 880219283

Integrate LLVM at llvm/llvm-project@5f1683ca1a4a

Updates LLVM usage to match
[5f1683ca1a4a](https://github.com/llvm/llvm-project/commit/5f1683ca1a4a)

PiperOrigin-RevId: 879769087

Automated Code Change

PiperOrigin-RevId: 879421320

[NFC] Make `LazyDagCache::QueryValue` non-recursive

Besides overall goodness in removing recursion in a compiler - avoid stack overflows in the case of large graphs - it also shows a small (~5%) perf improvement in some benchmarks.

PiperOrigin-RevId: 878636906

Merge pull request #3867 from xlsynth:cdleary/2026-02-19-resolve-tiv2…

Fix bug with match arm result of a type defined within the arm.

The issue was that in a case like
```
match X {
  u32:1 => u3:2,
  _ => {
    type InternalType = uN[Y + 1];
    InternalType:3
  }
}
```

the type unification of `u3:2` in the first arm would unify [`u3`, `InternalType`] when the constants that the latter depends on had not been collected yet due to later appearance.

Fixes #3892

PiperOrigin-RevId: 876504126

Automated Code Change

PiperOrigin-RevId: 875454978

Remove annotations from std.x that TIv2 does not require.

This is slightly conservative in that it does not remove them in situations where they might be desirable for readability or asserting the size of a parametric function result.

PiperOrigin-RevId: 874856499

Add io_printer_main tool.

This tool dumps information about IO operations (Send/Receive) from a scheduled XLS IR package. It can take either an IR file with embedded schedule information or an IR file combined with a separate schedule proto. The output shows the pipeline stage, direction, blocking status (for receives), and channel name for each IO node.

This can be helpful for determining relevant differences between two schedules.

PiperOrigin-RevId: 874120868

Automated Code Change

PiperOrigin-RevId: 873688680