Become a sponsor to Leo
Hi, I’m Leo
I build open-source tools for FPGA and embedded hardware development, with a focus on making advanced workflows easier to use across vendors and toolchains.
My main project is fpgacapZero, an open-source FPGA debug and automation toolkit. It includes cross-vendor JTAG debug cores such as embedded logic analyzer, embedded I/O, and JTAG-to-AXI bridge support, along with integrations for open-source FPGA tools and AI-assisted development workflows.
Sponsorship helps me spend more time improving documentation, testing more boards and cables, expanding backend support, and maintaining the project so others can use it in real hardware projects without starting from scratch.
Featured work
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lcapossio/fpgacapZero
fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
Python 75 -
lcapossio/fresca
Versatile multi-sensor temperature controller
C++ 11 -
lcapossio/hdldiagZero
An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram
Python 14 -
lcapossio/mjpegZero
Open source synthesizable MJPEG encoder written in behavioral Verilog 2001 with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs. Two operating modes: Full encodes with runtime qu…
Verilog 8 -
lcapossio/emacZero
Open-source Ethernet MAC with AXI4-Stream, AXI4-Lite CSR, MDIO, MII to RGMII support, jumbo frames, and stats.
Verilog 1 -
lcapossio/spacewire_light
SpaceWire Light
VHDL 3