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33rd ASAP 2022: Gothenburg, Sweden
- 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2022, Gothenburg, Sweden, July 12-14, 2022. IEEE 2022, ISBN 978-1-6654-8308-7
- Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar
:
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. 1-10 - Nan Wu
, Jiwon Lee, Yuan Xie, Cong Hao:
LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. 11-18 - Igor D. S. Miranda, Aman Arora
, Zachary Susskind, Luis Armando Quintanilla Villon, Rafael Fontella Katopodis, Diego Leonel Cadette Dutra
, Leandro Santiago de Araújo
, Priscila M. V. Lima, Felipe M. G. França
, Lizy K. John, Maurício Breternitz
:
LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks. 19-26 - Qilin Si
, Benjamin Carrion Schafer:
Optimizing Behavioral Near On-Chip Memory Computing Systems. 27-33 - Sheikh Faizan Qureshi, Stefan A. Damjancevic, Emil Matús, Dmitry Utyansky, Pieter van der Wolf, Gerhard P. Fettweis:
Efficient Synchronization for NR-REDCAP Implemented on a Vector DSP. 34-42 - Matteo Perotti, Matheus A. Cavalcante
, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini:
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. 43-51 - Yuzuki Mimura, Qiong Chang
, Tsutomu Maruyama:
Acceleration of video stabilization using embedded GPU. 52-59 - Paulo Cesar Santos, Bruno E. Forlin, Marco A. Z. Alves, Luigi Carro:
Aggressive Performance Improvement on Processing-in-Memory Devices by Adopting Hugepages. 60-63 - Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency. 64-71 - Maxime Christ, Florent de Dinechin, Frédéric Pétrot:
Low-precision logarithmic arithmetic for neural network accelerators. 72-79 - Ibrahim Ahmed, Sahil Parmar, Matthew Boyd, Michael Beidler, Kris Kang, Bill Liu, Kyle Roach, John Kim, Dennis Abts:
Answer Fast: Accelerating BERT on the Tensor Streaming Processor. 80-87 - Shashwat Khandelwal, Eashan Wadhwa, Shanker Shreejith
:
Deep Learning-based Embedded Intrusion Detection System for Automotive CAN. 88-92 - Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos
, Giorgos Dimitrakopoulos:
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks. 93-97 - Longlong Zhang, Xuebin Tang, Xiang Hu, Yuanxi Peng, Tong Zhou:
Full-BNN: A Low Storage and Power Consumption Time-Domain Architecture based on FPGA. 98-105 - Marc Rothmann, Mario Porrmann:
FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment. 106-114 - Eashan Wadhwa, Shashwat Khandelwal, Shanker Shreejith:
IMEC: A Memory-Efficient Convolution Algorithm For Quantised Neural Network Accelerators. 115-121 - Hugo Miomandre
, Jean-François Nezan, Daniel Ménard:
Design Space Exploration for Memory-Oriented Approximate Computing Techniques. 122-125 - Mulong Luo, G. Edward Suh:
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memorization. 126-130 - Hanqiu Chen, Cong Hao:
Mask-Net: A Hardware-efficient Object Detection Network with Masked Region Proposals. 131-138 - Matthias Nickel, Lester Kalms, Tim Häring, Diana Göhringer
:
High-Performance AKAZE Implementation Including Parametrizable and Generic HLS Modules. 139-147 - Rashmi Agrawal, Ji Yang, Haris Javaid:
Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains. 148-155 - Julian Haase, Sebastian Jaster
, Elke Franz, Diana Göhringer
:
Secure Communication Protocol for Network-on-Chip with Authenticated Encryption and Recovery Mechanism. 156-160 - Kari Hepola
, Joonas Multanen, Pekka Jääskeläinen
:
OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. 161-165
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