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46th DAC 2009: San Francisco, CA, USA
- Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009. ACM 2009, ISBN 978-1-60558-497-3
Panel
- Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl:
System prototypes: virtual, hardware or hybrid? 1-3
Mechanisms for surviving uncertainty: opportunities and prospects
- Keith A. Bowman
, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. 4-7 - Emre Tuncer, Jordi Cortadella, Luciano Lavagno:
Enabling adaptability through elastic clocks. 8-10 - Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken:
Addressing design margins through error-tolerant circuits. 11-12
Combating non-idealities in static timing analysis
- Ravikishore Gandikota, Li Ding, Peivand Tehrani, David T. Blaauw:
Worst-case aggressor-victim alignment with current-source driver models. 13-18 - David D. Ling, Chandu Visweswariah, Peter Feldmann, Soroush Abbaspour:
A moment-based effective characterization waveform for static timing analysis. 19-24 - Shihheng Tsai, Chung-Yang Huang:
A false-path aware formal static timing analyzer considering simultaneous input transitions. 25-30
High-performance platforms: advances in system-level exploration and optimization
- Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions. 31-36 - Zhonglei Wang, Andreas Herkersdorf, Wolfgang Haberl, Martin Wechs:
SysCOLA: a framework for co-development of automotive software and system platform. 37-42 - Michael Glaß
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. 43-46 - Jungseob Lee, Nam Sung Kim:
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. 47-50
Novel design and verification methodologies
- Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study. 51-56 - Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung:
Selective wordline voltage boosting for caches to manage yield under process variations. 57-62 - Kun Yuan, Katrina Lu, David Z. Pan:
Double patterning lithography friendly detailed routing with redundant via consideration. 63-66 - David Abercrombie, Fedor Pikus, Cosmin Cazan:
Use of lithography simulation for the calibration of equation-based design rule checks. 67-70
Design and optimization of nanocircuits
- Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra:
Carbon nanotube circuits in the presence of carbon nanotube density variations. 71-76 - M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli:
Decoding nanowire arrays fabricated with the multi-spacer patterning technique. 77-82 - Marek A. Bawiec, Maciej Nikodem
Boolean logic function synthesis for generalised threshold gate circuits. 83-86 - Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang:
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. 87-90
Panel
- Eshel Haritan, Andreas Kuehlmann, Tina Jones, John Epperheimer, Jan M. Rabaey, Rahul Razdan, Naveen Gupta:
EDA in flux: should I stay or should I go? 91-92
Dawn of the 22nm design era - yes we can!
- Shekhar Borkar:
Design perspectives on 22nm CMOS and beyond. 93-94 - Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi:
Creating an affordable 22nm node using design-lithography co-optimization. 95-96 - Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta:
Device/circuit interactions at 22nm technology node. 97-102 - Carl J. Anderson:
Beyond innovation: dealing with the risks and complexity of processor design in 22nm. 103
Statistical methods in static timing analysis
- Lerong Cheng, Puneet Gupta
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. 104-109 - Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama:
A Gaussian mixture model for statistical timing analysis. 110-115 - James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi:
A stochastic jitter model for analyzing digital timing-recovery circuits. 116-121 - Jinjun Xiong
Statistical ordering of correlated timing quantities and its application for path ranking. 122-125 - Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik:
A parametric approach for handling local variation effects in timing analysis. 126-129
Profiling, test and debug of embedded systems
- Karthik Shankar, Roman L. Lysecky:
Non-intrusive dynamic application profiling for multitasked applications. 130-135 - Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang:
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC. 136-141 - Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra:
Generating test programs to cover pipeline interactions. 142-147 - Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su:
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core. 148-153
Low-power design and analysis techniques
- Vineeth Veetil, Dennis Sylvester, David T. Blaauw, Saumil Shah, Steffen Rochel:
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. 154-159 - Eli Arbel, Cindy Eisner, Oleg Rokhlenko:
Resurrecting infeasible clock-gating functions. 160-165 - Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. 166-171 - Cedric Walravens, Yves Vanderperren, Wim Dehaene:
ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models. 172-177
Design integrity challenges
- Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang:
GPU friendly fast Poisson solver for structured power grid network analysis. 178-183 - Nahi H. Abdul Ghani, Farid N. Najm:
Fast vectorless power grid verification using an approximate inverse technique. 184-189 - Görschwin Fey, André Sülflow, Rolf Drechsler:
Computing bounds for fault tolerance using formal techniques. 190-195 - Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
Clock skew optimization via wiresizing for timing sign-off covering all process corners. 196-201
Panel
- Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork:
Moore's Law: another casualty of the financial meltdown? 202-203
Verifying an SOC monster: whose job is it anyway?
- Pradip A. Thaker:
Holistic verification: myth or magic bullet? 204-208 - Warren Stapleton, Paul Tobin:
Verification problems in reusing internal design components. 209-211 - Dave Whipp:
Exploiting "architecture for verification" to streamline the verification process. 212-215 - Eric Chesters:
Role of the verification team throughout the ASIC development life cycle. 216-219
Timing simulation: optimized embedded software and MPSOCs
- Zhonglei Wang, Andreas Herkersdorf:
An efficient approach for system-level timing simulation of compiler-optimized embedded software. 220-225 - Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev:
MPTLsim: a simulator for X86 multicore processors. 226-231 - Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou:
Trace-driven workload simulation method for Multiprocessor System-On-Chips. 232-237
Advances in embedded system modeling and optimization
- Lang Lin, Wayne P. Burleson:
Analysis and mitigation of process variation impacts on Power-Attack Tolerance. 238-243 - Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra:
Evaluating design trade-offs in customizable processors. 244-249 - Haris Javaid, Sri Parameswaran
A design flow for application specific heterogeneous pipelined multiprocessor systems. 250-253 - Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner:
Xquasher: a tool for efficient computation of multiple linear expressions. 254-257
Interconnect optimization for emerging technologies
- Cliff Chiung-Yu Lin, Yao-Wen Chang:
ILP-based pin-count aware design methodology for microfluidic biochips. 258-263 - Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan:
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. 264-269 - Robert Wille
BDD-based synthesis of reversible logic for large functions. 270-275
Design flexibility: bend it, shape it, anyway you want it!
- Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem. 276-281 - Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah:
A computing origami: folding streams in FPGAs. 282-287 - Dmitry Bufistov, Jordi Cortadella
Retiming and recycling for elastic systems with early evaluation. 288-291 - Marc Galceran Oms, Jordi Cortadella
Speculation in elastic systems. 292-295
Panel
- Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels:
DFM: don't care or competitive weapon? 296-297
Emerging technologies: blue-sky research or CMOS replacement?
- Jeff Welser:
The semiconductor industry's nanoelectronics research initiative: motivation and challenges. 298-300 - Ken Uchida:
Single-electron devices for ubiquitous and secure computing applications. 301-303 - Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. 304-309 - Kelin J. Kuhn:
CMOS scaling beyond 32nm: challenges and opportunities. 310-313
Routing: from chip to package
- Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Yao-Hsin Chou:
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction. 314-319 - Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
GRIP: scalable 3D global routing using integer programming. 320-325 - Hui Kong, Tan Yan, Martin D. F. Wong
Automatic bus planner for dense PCBs. 326-331 - Tan Yan, Martin D. F. Wong
A correct network flow model for escape routing. 332-335 - Jia-Wei Fang, Martin D. F. Wong
Flip-chip routing with unified area-I/O pad assignments for package-board co-design. 336-339
Speed path identification and silicon debug
- Jinjun Xiong
Statistical multilayer process space coverage for at-speed test. 340-345 - Nicholas Callegari, Li-C. Wang, Pouria Bastani:
Speedpath analysis based on hypothesis pruning and ranking. 346-351 - Xiao Liu, Qiang Xu
Interconnection fabric design for tracing signals in post-silicon validation. 352-357 - Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Online cache state dumping for processor debug. 358-363
Analog/RF simulation and statistical modeling
- Xin Li:
Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression. 364-369 - Amit Mehrotra, Abhishek Somani:
A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian. 370-375 - Jaeha Kim, Jihong Ren, Mark A. Horowitz:
Stochastic steady-state and AC analyses of mixed-signal systems. 376-381 - Wei Dong, Peng Li:
Parallelizable stable explicit numerical integration for efficient circuit simulation. 382-385 - Hong Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li:
Efficient design-specific worst-case corner extraction for integrated circuits. 386-389
Recent advances in timing, ECO and logic optimization
- Mihir R. Choudhury, Kartik Mohanram:
Timing-driven optimization using lookahead logic circuits. 390-395 - Kuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu:
Simulation and SAT-based Boolean matching for large Boolean networks. 396-401 - Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang:
New spare cell design for IR drop minimization in Engineering Change Order. 402-407 - Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes. 408-411 - Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo:
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. 412-415
Panel
- Patrick Groeneveld, Rob A. Rutenbar
Oil fields, hedge funds, and drugs. 416-417
Computation in the post-Turing era
- Luis von Ahn:
Human computation. 418-419 - Dileep George:
How to make computers that work like the brain. 420-423
Advances in physical synthesis
- Shiyan Hu, Zhuo Li, Charles J. Alpert:
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. 424-429 - Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao:
Spare-cell-aware multilevel analytical placement. 430-435 - Jackey Z. Yan, Natarajan Viswanathan, Chris Chu:
Handling complexities in modern large-scale mixed-size placement. 436-441 - Ashutosh Chakraborty, Anurag Kumar, David Z. Pan:
RegPlace: a high quality open-source placement framework for structured ASICs. 442-447
Jumping the high-level verification hurdle
- Gabriel Marcilio, Luiz C. V. dos Santos
A novel verification technique to uncover out-of-order DUV behaviors. 448-453 - Alon Gluska, Lior Libis:
Shortening the verification cycle with synthesizable abstract models. 454-459 - Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma:
Non-cycle-accurate sequential equivalence checking. 460-465 - Benny Godlin, Ofer Strichman
Regression verification. 466-471
Thermal optimization
- Yufu Zhang, Ankur Srivastava
Accurate temperature estimation using noisy thermal sensors. 472-477 - Ryan Cochran, Sherief Reda:
Spectral techniques for high-resolution thermal characterization with limited sensor data. 478-483 - Ramkumar Jayaseelan, Tulika Mitra:
Dynamic thermal management via architectural adaptation. 484-489 - Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration. 490-495
Novel techniques to minimize circuit failure
- Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi:
SRAM parametric failure analysis. 496-501 - Weiguang Sheng, Liyi Xiao, Zhigang Mao:
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. 502-507 - Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Improving testability and soft-error resilience through retiming. 508-513 - Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng:
Statistical reliability analysis under process variation and aging effects. 514-519
Panel
- Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong:
Guess, solder, measure, repeat: how do I get my mixed-signal chip right? 520-521
Multicore computing and EDA
- Charles E. Leiserson:
The Cilk++ concurrency platform. 522-527 - David H. Bailey:
Misleading performance claims in parallel computations. 528-533 - Steven P. Levitan, Donald M. Chiarulli:
Massively parallel processing: it's déjà vu all over again. 534-538
Layout-based variability modeling and optimization
- Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
Provably good and practically efficient algorithms for CMP dummy fill. 539-544 - Dragoljub Gagi Drmanac, Frank Liu, Li-C. Wang:
Predicting variability in nanoscale lithography processes. 545-550 - Yun Ye, Frank Liu, Min Chen, Yu Cao:
Variability analysis under layout pattern-dependent rapid-thermal annealing process. 551-556
Advances in core verification techniques
- Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Event-driven gate-level simulation with GP-GPUs. 557-562 - Himanshu Jain, Edmund M. Clarke:
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts. 563-568 - Kuntal Nanshi, Fabio Somenzi:
Constraints in one-to-many concretization for abstraction refinement. 569-574
Future interconnect technologies: how do on-chip networks evolve?
- Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun:
Spectrum: a hybrid nanophotonic-electric on-chip network. 575-580 - Sudeep Pasricha:
Exploring serial vertical interconnects for 3D ICs. 581-586 - Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang:
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. 587-592
Robust analog system design
- Mark Po-Hung Lin
Thermal-driven analog placement considering device matching. 593-598 - Yan Li, Vladimir Stojanovic:
Yield-driven iterative robust circuit optimization algorithm. 599-604 - Xuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli:
Contract-based system-level composition of analog circuits. 605-610
WACI: wild and crazy ideas
- Atanu Chattopadhyay, Zeljko Zilic:
Serial reconfigurable mismatch-tolerant clock distribution. 611-612 - José Luis Ayala
Thermal-aware data flow analysis. 613-614 - Mustafa Altun, Marc D. Riedel
Nanoscale digital computation through percolation. 615-616 - Bo Marr, Arindam Basu
A learning digital computer. 617-618 - Shimeng Huang, Joseph Oresko, Yuwen Sun, Allen C. Cheng:
Programmable neural processing on a smartdust. 619-620 - Andrew DeOrio, Valeria Bertacco:
Human computing for EDA. 621-622 - Andreas Raabe, Rastislav Bodík:
Synthesizing hardware from sketches. 623-624 - Pai H. Chou:
Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity. 625-626
The tool shows that my design is wrong, but where is the bug?
- Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi:
Debugging from high level down to gate level. 627-630 - Andreas G. Veneris, Sean Safarpour:
The day Sherlock Holmes decided to do EDA. 631-634 - Valeria Bertacco:
Debugging strategies for mere mortals. 635-638 - Gila Kamhi, Alexander Novakovsky, Andreas Tiemeyer, Adriana Wolffberg:
MAGENTA: transaction-based statistical micro-architectural root-cause analysis. 639-643 - Michael Siegel, Adriana Maggiore, Christian Pichler:
Untwist your brain: efficient debugging and diagnosis of complex assertions. 644-647 - Rajeev K. Ranjan, Claudionor Coelho, Sebastian Skalberg:
Beyond verification: leveraging formal for debugging. 648-651
Embedded system design for low-power
- Mian Dong, Yung-Seok Kevin Choi, Lin Zhong:
Power modeling of graphical user interfaces on OLED displays. 652-657 - Veera Papirla, Chaitali Chakrabarti:
Energy-aware error control coding for Flash memories. 658-663 - Gaurav Dhiman, Raid Zuhair Ayoub, Tajana Rosing:
PDRAM: a hybrid PRAM and DRAM main memory system. 664-469 - Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy:
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. 670-675
Hardware authentication, characterization and trusted design
- Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
A physical unclonable function defined using power distribution system equivalent resistance variations. 676-681 - Daniel Y. Deng, Andrew H. Chan, G. Edward Suh
Hardware authentication leveraging performance limits in detailed simulations and emulations. 682-687 - Miodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey:
Hardware Trojan horse detection using gate-level characterization. 688-693 - Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph:
Process variation characterization of chip-level multiprocessors. 694-697 - Junjun Gu, Gang Qu, Qiang Zhou:
Information hiding for trusted system design. 698-701
Targeted test and diagnosis
- Feng Yuan, Qiang Xu:
On systematic illegal state identification for pseudo-functional testing. 702-707 - Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton:
Automated failure population creation for validating integrated circuit diagnosis methods. 708-713 - Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin:
Fault models for embedded-DRAM macros. 714-719 - Ender Yilmaz, Sule Ozev:
Adaptive test elimination for analog/RF circuits. 720-725
Challenges of memory-aware design for embedded systems
- Heiko Falk:
WCET-aware register allocation based on graph coloring. 726-731 - Heiko Falk, Jan C. Kleinsorge:
Optimal static WCET-aware scratchpad allocation of program code. 732-737 - Vladimir Uzelac, Aleksandar Milenkovic
A real-time program trace compressor utilizing double move-to-front method. 738-743 - José Baiocchi, Bruce R. Childers:
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators. 744-749
Panel
- Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach:
From milliwatts to megawatts: system level power challenge. 750-751
Parasitic extraction in the face of process variability
- Wenwen Chai, Dan Jiao, Cheng-Kok Koh:
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. 752-757 - Wenjian Yu, Chao Hu, Wangyang Zhang:
Variational capacitance extraction of on-chip interconnects based on continuous surface model. 758-763 - Fang Gong, Hao Yu, Lei He:
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. 764-769 - Tarek A. El-Moselhy, Ibrahim M. Elfadel, Bill Dewey:
An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes. 770-775
Scheduling, allocation and reliability
- Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha:
Throughput optimal task allocation under thermal constraints for multi-core processors. 776-781 - Shaobo Liu, Qing Wu, Qinru Qiu:
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems. 782-787 - Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack. 788-793 - Hochang Jang, Taewhan Kim:
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. 794-799
Network-on-chip advances for power, reliability and the memory bottleneck
- Wooyoung Jang, David Z. Pan:
An SDRAM-aware router for Networks-on-Chip. 800-805 - Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. 806-811 - David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester:
Vicis: a reliable network for unreliable silicon. 812-817 - Siddharth Garg, Diana Marculescu
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. 818-821 - Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
NoC topology synthesis for supporting shutdown of voltage islands in SoCs. 822-825
Leveraging parallelism in FPGAs and multicore systems
- Yoonjin Kim, Rabi N. Mahapatra:
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems. 826-831 - Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng:
Multicore parallel min-cost flow algorithm for CAD applications. 832-837 - Scott Cromar, Jaeho Lee, Deming Chen:
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. 838-843 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
FPGA-based accelerator for the verification of leading-edge wireless systems. 844-847 - Chen Huang, Frank Vahid:
Transmuting coprocessors: dynamic loading of FPGA coprocessors. 848-851
Space and time management in embedded applications
- Mahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara:
Dynamic thread and data mapping for NoC based CMPs. 852-857 - Yuan-Hao Chang
A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. 858-863 - Soheil Samii, Petru Eles, Zebo Peng, Anton Cervin:
Quality-driven synthesis of embedded multi-mode control systems. 864-869 - Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury:
Context-sensitive timing analysis of Esterel programs. 870-873 - Haibo Zeng, Wei Zheng, Marco Di Natale, Arkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli:
Scheduling the FlexRay bus using optimization techniques. 874-877
Panel
- Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti:
The wild west: conquest of complex hardware-dependent software design. 878-879
Technologies for green data centers
- Jonathan D. Ellithorpe, Zhangxi Tan, Randy H. Katz:
Internet-in-a-Box: emulating datacenter network architectures using FPGAs. 880-883 - Prith Banerjee, Chandrakant D. Patel, Cullen E. Bash, Parthasarathy Ranganathan:
Sustainable data centers: enabled by supply and demand side management. 884-887 - Dilip D. Kandlur, Tom W. Keller:
Green data centers and hot chips. 888-890
How to improve your memory
- Erick Amador, Renaud Pacalet, Vincent Rezard:
Optimum LDPC decoder: a memory architecture problem. 891-896 - Zhiguo Ge, Tulika Mitra, Weng-Fai Wong:
A DVS-based pipelined reconfigurable instruction memory. 897-902 - Talal Bonny
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors. 903-906 - Sanghyuk Jung, Jin Hyuk Kim, Yong Ho Song:
Hierarchical architecture of flash-based storage systems for high performance and durability. 907-910
Scheduling in time and space
- Marc Geilen
Reduction techniques for synchronous dataflow graphs. 911-916 - Hamid Shojaei, Amir Hossein Ghamarian, Twan Basten, Marc Geilen, Sander Stuijk, Rob Hoes:
A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management. 917-922 - William Plishker, Nimish Sane, Shuvra S. Bhattacharyya:
Mode grouping for more effective generalized scheduling of dynamic dataflow applications. 923-926 - Jian Chen, Lizy Kurian John:
Efficient program scheduling for heterogeneous multi-core processors. 927-930
Heuristic approaches to hardware optimization
- Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita:
Polynomial datapath optimization using partitioning and compensation heuristics. 931-936 - Insup Shin, Seungwhun Paik, Youngsoo Shin:
Register allocation for high-level synthesis using dual supply voltages. 937-942 - Yifang Liu, Jiang Hu:
GPU-based parallelization for fast circuit optimization. 943-946 - Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha:
Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors. 947-950
Model order reduction techniques and applications
- Jorge Fernandez Villena, Luís Miguel Silveira
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques. 951-956 - N. Wong:
An efficient passivity test for descriptor systems via canonical projector techniques. 957-962 - Zhenhai Zhu:
A parameterized mask model for lithography simulation. 963-968
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