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Ching-Yu Chin
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2010 – 2019
- 2017
- [c8]Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen:
An analytical placer for heterogeneous FPGAs via rough-placed packing. VLSI-DAT 2017: 1-4 - 2015
- [j5]Po-Cheng Pan
, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin:
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1373-1386 (2015) - [c7]Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen:
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. ISPD 2015: 149-156 - 2014
- [j4]Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin:
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation. ACM Trans. Design Autom. Electr. Syst. 20(1): 3:1-3:23 (2014) - [j3]Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen:
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1404-1415 (2014) - 2013
- [j2]Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani:
Escaped Boundary Pins Routing for High-Speed Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 381-391 (2013) - [c6]Ching-Yu Chin, Po-Cheng Pan
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD 2013: 40-47 - 2012
- [c5]Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen:
A fast thermal aware placement with accurate thermal analysis based on Green function. ASP-DAC 2012: 425-430 - 2011
- [j1]Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang:
A Novel Test Flow for One-Time-Programming Applications of NROM Technology. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2170-2183 (2011) - [c4]Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani:
On routing fixed escaped boundary pins for high speed boards. DATE 2011: 461-466 - 2010
- [c3]Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin:
Mathematical yield estimation for two-dimensional-redundancy memory arrays. ICCAD 2010: 235-240
2000 – 2009
- 2009
- [c2]Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin:
Fault models for embedded-DRAM macros. DAC 2009: 714-719 - [c1]Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao:
A novel test flow for one-time-programming applications of NROM technology. ITC 2009: 1-9
Coauthor Index
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