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ITC 2009: Austin, TX, USA
- Gordon W. Roberts, Bill Eklow:
2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4868-5 - Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward:
Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. 1-10 - Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson:
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. 1-10 - Yen-Tzu Lin, Ronald D. Blanton:
Test effectiveness evaluation through analysis of readily-available tester data. 1-10 - Rama Gudavalli, W. Robert Daasch, Phil Nigh, Douglas Heaberlin:
Application of non-parametric statistics of the parametric response for defect diagnosis. 1-10 - Steve Sunter, Kenneth P. Parker:
Testing bridges to nowhere - combining Boundary Scan and capacitive sensing. 1-10 - Jay J. Nejedlo, Rahul Khanna:
Intel® IBIST, the full vision realized. 1-11 - Sergei Devadze
, Artur Jutman
Fast extended test access via JTAG and FPGAs. 1-7 - Philip B. Geiger, Steve Butkovich:
Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry. 1-10 - Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang
Minimizing outlier delay test cost in the presence of systematic variability. 1-10 - Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy:
Accurate measurement of small delay defect coverage of test patterns. 1-10 - Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang:
Capture power reduction using clock gating aware test generation. 1-9 - Desta Tadesse, Joel Grodstein, R. Iris Bahar
AutoRex: An automated post-silicon clock tuning tool. 1-10 - Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu:
Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family. 1-10 - Janine Chen, Li-C. Wang
Data learning techniques and methodology for Fmax prediction. 1-10 - Ender Yilmaz, Afsaneh Nassery, Sule Ozev, Erkan Acar:
Built-in EVM measurement for OFDM transceivers using all-digital DFT. 1-10 - Bobby Lai, Chris Rivera, Khurram Waheed:
Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers. 1-7 - Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations. 1-10 - Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Fault diagnosis for embedded read-only memories. 1-10 - Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao:
A novel test flow for one-time-programming applications of NROM technology. 1-9 - Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu:
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. 1-10 - Franco Stellari, Peilin Song, John Sylvestri, D. Miles, Orazio P. Forlenza, Donato O. Forlenza:
On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC). 1-10 - Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson:
Voltage transient detection and induction for debug and test. 1-10 - Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick:
Cache-resident self-testing for I/O circuitry. 1-8 - Feng Yuan, Qiang Xu
Compression-aware pseudo-functional testing. 1-10 - Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Compression based on deterministic vector clustering of incompatible test cubes. 1-10 - Xiao Liu, Qiang Xu
On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment. 1-10 - Albert Yeh, Jesse Chou, Max Lin:
An economical, precise and limited access In-Circuit Test method for pulse-width modulation (PWM) circuits. 1-9 - Chwee Liong Tee, Tzyy Haw Tan, Chin Chuan Ng:
Augmenting board test coverage with new intel powered opens boundary scan instruction. 1-10 - Xin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird:
An outlier detection based approach for PCB testing. 1-10 - Hideo Okawara:
SSC applied serial ATA signal generation and analysis by analog tester resources. 1-9 - Takahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida:
A robust method for identifying a deterministic jitter model in a total jitter distribution. 1-10 - Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu:
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing. 1-10 - Timothy Daniel Lyons:
A timestamping method using reduced cost ADC hardware. 1-8 - Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta:
A novel architecture for on-chip path delay measurement. 1-10 - Haoxing Ren, Mary P. Kusko, Victor N. Kravets, Rona Yaari:
Low cost test point insertion without using extra registers for high performance design. 1-8 - Lin Huang, Qiang Xu
Test economics for homogeneous manycore systems. 1-10 - Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty
Physical defect modeling for fault insertion in system reliability test. 1-10 - Luca Testa
BIST scheme for RF VCOs allowing the self-correction of the cut. 1-10 - Brendan Mullane
A2DTest: A complete integrated solution for on-chip ADC self-test and analysis. 1-10 - Masashi Shimanouchi, Mike P. Li, Daniel Chow:
New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing. 1-8 - Muzaffer O. Simsir, Niraj K. Jha:
Thermal characterization of BIST, scan design and sequential test methodologies. 1-9 - Hsuan-Chung Ko, Deng-Yao Chang, Cheng-Nan Hu:
Cost-effective approach to improve EMI yield loss. 1-8 - David C. Keezer
A development platform and electronic modules for automated test up to 20 Gbps. 1-11 - M. Enamul Amyeen, Srikanth Venkataraman, Mun Wai Mak:
Microprocessor system failures debug and fault isolation methodology. 1-10 - Junpei Nonaka, Toshio Ishiyama, Kazuki Shigeta:
Design for failure analysis inserting replacement-type observation points for LVP. 1-10 - Nicholas Callegari, Li-C. Wang
Feature based similarity search with application to speedpath analysis. 1-10 - Chia-Ling Chang, Charles H.-P. Wen
Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. 1-8 - Min Li, Michael S. Hsiao:
An ant colony optimization technique for abstraction-guided state justification. 1-10 - Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu:
Diagnostic test generation for transition faults using a stuck-at ATPG tool. 1-9 - Ozgur Sinanoglu
X-alignment techniques for improving the observability of response compactors. 1-10 - Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak:
An industrial case study for X-canceling MISR. 1-10 - Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba:
Test point insertion using functional flip-flops to drive control points. 1-10 - Jocelyn Moreau, Thomas Droniou, Philippe Lebourg, Paul Armagnat:
Running scan test on three pins: yes we can! 1-10 - Tseng-Chin Luo, Mango Chia-Tso Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young:
A novel array-based test methodology for local process variation monitoring. 1-9 - Swapneel Donglikar, Mainak Banga, Maheshwar Chandrasekar, Michael S. Hsiao:
Fast circuit topology based method to configure the scan chains in Illinois Scan architecture. 1-10 - Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram
Tolerance of performance degrading faults for effective yield improvement. 1-10 - Erik Jan Marinissen
Testing 3D chips containing through-silicon vias. 1-11 - Adam W. Ley:
Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture. 1-10 - Len Losik:
Eliminating product infant mortality failures using prognostic analysis. 1 - Sukeshwar Kannan, Bruce C. Kim:
Automatic diagnostic tool for Analog-Mixed Signal and RF load boards. 1 - Michele Portolan
Scalable and efficient integrated test architecture. 1 - Shiue-Tsung Shen, Wei-Hsiao Liu, Chien-Mo James Li, I-Chun Cheng
Very-Low-Voltage testing of amorphous silicon TFT circuits. 1 - Po-Han Wu, Jiann-Chyi Rau:
Low power multi-chains encoding scheme for SoC in low-cost environment. 1 - Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Power and thermal constrained test scheduling. 1 - Bing-Chuan Bai
Power scan: DFT for power switches in VLSI designs. 1 - Ken Posse, Al Crouch, Jeff Rearick:
IEEE P1687 IJTAG a presentation of current technology. 1 - Heiko Ehrenberg:
Test Mode Entry and Exit Methods for IEEE P1581 compliant devices. 1 - Boyon Kim, Il-Chan Park, Giseob Song, Wooseong Choi, Byeong-Yun Kim, Kyutaek Lee, Chi-Young Choi:
A novel multisite testing techniques by using frequency synthesizer. 1 - Youhua Shi
Design-for-secure-test for crypto cores. 1 - Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet
Non-invasive RF built-in testing using on-chip temperature sensors. 1 - Pierre-Didier Mauroux, Arnaud Virazel
NAND flash testing: A preliminary study on actual defects. 1 - Bilal El Kassir, Christophe Kelma, Bernard Jarry, Michel Campovecchio:
Built-in Self Test for Error Vector Magnitude measurement of RF transceiver. 1 - Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng:
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. 1 - Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen
Portable simulation/emulation stimulus on an industrial-strength SoC. 1 - Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto:
Test infrastructures evaluation at transaction level. 1 - Xiao Liu, Qiang Xu
Trace signal selection for debugging electrical errors in post-silicon validation. 1 - Adam W. Ley:
Defect coverage of non-intrusive board tests (NBT): What does it mean when a non-intrusive board test passes? 1 - Kenneth P. Parker, Jeff Burgess:
What is IEEE P1149.8.1 and why? 1 - Matthias Kamm:
Manufacturing data: Maximizing value using component-to-system analysis. 1 - Jim Vana, Alexander Barr, Richard Scherer, Abhay Joshi:
High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols. 1 - Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test access mechanism for multiple identical cores. 1-10
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