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55th DAC 2018: San Francisco, CA, USA
- Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018. ACM 2018, ISBN 978-1-5386-4114-9
- Hossein Sayadi, Nisarg Patel, Sai Manoj P. D.
, Avesta Sasan, Setareh Rafatirad, Houman Homayoun:
Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification. 1:1-1:6 - Bita Darvish Rouhani, M. Sadegh Riazi, Farinaz Koushanfar
Deepsecure: scalable provably-secure deep learning. 2:1-2:6 - Song Bian, Masayuki Hiromoto, Takashi Sato
DWE: decrypting learning with errors with errors. 3:1-3:6 - Weizhe Hua, Zhiru Zhang
Reverse engineering convolutional neural networks through side-channel information leaks. 4:1-4:6 - Daekyu Park, Donghyun Kang
OFTL: ordering-aware FTL for maximizing performance of the journaling file system. 5:1-5:6 - Chundong Wang, Sudipta Chattopadhyay:
LAWN: boosting the performance of NVMM file system through reducing write amplification. 6:1-6:6 - Fei Wu, Jiaona Zhou, Shunzhuo Wang, Yajuan Du, Chengmo Yang, Changsheng Xie:
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs. 7:1-7:6 - Won-Kyung Kang, Sungjoo Yoo:
Dynamic management of key states for reinforcement learning-assisted garbage collection to reduce long tail latency in SSD. 8:1-8:6 - Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang:
WB-trees: a meshed tree representation for FinFET analog layout designs. 9:1-9:6 - Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. 10:1-10:6 - Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Multi-objective bayesian optimization for analog/RF circuit synthesis. 11:1-11:6 - Kaige Jia, Zheyu Liu, Qi Wei, Fei Qiao, Xinjun Liu, Yi Yang, Hua Fan, Huazhong Yang:
Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors. 12:1-12:6 - Hyeon Uk Sim, Saken Kenzhegulov, Jongeun Lee:
DPS: dynamic precision scaling for stochastic computing-based deep neural networks. 13:1-13:6 - Mateja Putic, Swagath Venkataramani, Schuyler Eldridge
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. 14:1-14:6 - Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, Chuanjin Richard Shi:
Exploring the programmability for deep learning processors: from architecture to tensorization. 15:1-15:6 - Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu
LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. 16:1-16:6 - Brandon Reagen, Udit Gupta, Lillian Pentecost
Ares: a framework for quantifying the resilience of deep neural networks. 17:1-17:6 - Zihao Liu, Tao Liu, Wujie Wen, Lei Jiang, Jie Xu
DeepN-JPEG: a deep neural network favorable JPEG-based image compression framework. 18:1-18:6 - Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg:
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators. 19:1-19:6 - Sayeh Sharify, Alberto Delmas Lascorz, Kevin Siu, Patrick Judd, Andreas Moshovos:
Loom: exploiting weight and activation precisions to accelerate convolutional neural networks. 20:1-20:6 - Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. 21:1-21:6 - Mohammad Reza Mahmoodi, Dmitri B. Strukov
An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology. 22:1-22:6 - Lennart Bamberg
Coding approach for low-power 3D interconnects. 23:1-23:6 - Anthony Agnesina, Amanvir Sidana, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim
A novel 3D DRAM memory cube architecture for space applications. 24:1-24:6 - Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
A general graph based pessimism reduction framework for design optimization of timing closure. 25:1-25:6 - Grace Li Zhang
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. 26:1-26:6 - Shaoheng Luo, Cheng Zhuo, Houle Gan:
Noise-aware DVFS transition sequence optimization for battery-powered IoT devices. 27:1-27:6 - Divya Prasad, Saurabh Sinha
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. 28:1-28:6 - Peter Munk
Semi-automatic safety analysis and optimization. 29:1-29:6 - Cumhur Erkan Tuncali, James Kapinski, Hisahiro Ito, Jyotirmoy V. Deshmukh:
Reasoning about safety of learning-enabled components in autonomous cyber-physical systems. 30:1-30:6 - Kosuke Watanabe, Eunsuk Kang, Chung-Wei Lin, Shinichi Shiraishi:
Runtime monitoring for safety of intelligent vehicles. 31:1-31:6 - Markus Miettinen, Thien Duc Nguyen, Ahmad-Reza Sadeghi, N. Asokan:
Revisiting context-based authentication in IoT. 32:1-32:6 - Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh, Farinaz Koushanfar
MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers. 33:1-33:6 - Donghyun Kwon, Kuenwhee Oh, Junmo Park, Seungyong Yang, Yeongpil Cho, Brent ByungHoon Kang, Yunheung Paek:
Hypernel: a hardware-assisted framework for kernel protection without nested paging. 34:1-34:6 - Salessawi Ferede Yitbarek, Todd M. Austin:
Reducing the overhead of authenticated memory encryption using delta encoding and ECC memory. 35:1-35:6 - Andrew B. Kahng:
Reducing time and effort in IC implementation: a roadmap of challenges and solutions. 36:1-36:6 - Shankar Sadasivam, Zhuo Chen, Jinwon Lee, Rajeev Jain:
Efficient reinforcement learning for automating human decision-making in SoC design. 37:1-37:6 - Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Pierce Chuang, Leland Chang:
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. 38:1-38:6 - Majed Valad Beigi, Gokhan Memik:
Thermal-aware optimizations of reRAM-based neuromorphic computing systems. 39:1-39:6 - Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph:
Compiler-guided instruction-level clock scheduling for timing speculative processors. 40:1-40:6 - Yunfei Gu, Dengxue Yan, Vaibhav Verma
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. 41:1-41:6 - Veni Mohan, Akhilesh Iyer, John Sartori:
Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems. 42:1-42:6 - An Zou, Jingwen Leng, Xin He, Yazhou Zu, Vijay Janapa Reddi, Xuan Zhang
Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators. 43:1-43:6 - Stephan Held, Benjamin Rockel:
Exact algorithms for delay-bounded steiner arborescences. 44:1-44:6 - Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. 45:1-45:6 - Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang:
Obstacle-avoiding open-net connector with precise shortest distance estimation. 46:1-46:6 - Chien-Pang Lu, Iris Hui-Ru Jiang:
COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. 47:1-47:6 - Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat
A machine learning framework to identify detailed routing short violations from a placed netlist. 48:1-48:6 - Hai-Juan Yu, Yao-Wen Chang:
DSA-friendly detailed routing considering double patterning and DSA template assignments. 49:1-49:6 - Cunxi Yu
Developing synthesis flows without human knowledge. 50:1-50:6 - Ai Quoc Dao, Nian-Ze Lee
Efficient computation of ECO patch functions. 51:1-51:6 - Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. 52:1-52:6 - Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
SAT based exact synthesis using DAG topology families. 53:1-53:6 - Sanbao Su, Yi Wu, Weikang Qian:
Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis. 54:1-54:6 - Soheil Hashemi, Hokchhay Tann, Sherief Reda:
BLASYS: approximate logic synthesis using boolean matrix factorization. 55:1-55:6 - Seonbong Kim, Joon-Sung Yang:
Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system. 56:1-56:6 - Chun-Feng Wu
Improving runtime performance of deduplication system with host-managed SMR storage drives. 57:1-57:6 - Wen Wen
Wear leveling for crossbar resistive memory. 58:1-58:6 - Wenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie:
RADAR: a 3D-reRAM based DNA alignment accelerator architecture. 59:1-59:6 - Shunning Jiang, Berkin Ilbeyi, Christopher Batten:
Mamba: closing the performance gap in productive hardware development frameworks. 60:1-60:6 - Angie Wang, Paul Rigge, Adam M. Izraelevitz, Chick Markley, Jonathan Bachrach, Borivoje Nikolic
ACED: a hardware library for generating DSP systems. 61:1-61:6 - Venkata Yaswanth Raparti, Sudeep Pasricha:
PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon era. 62:1-62:6 - Heba Khdr
Aging-constrained performance optimization for multi cores. 63:1-63:6 - Johannes Obermaier
A measurement system for capacitive PUF-based security enclosures. 64:1-64:6 - Shaza Zeitouni, David Gens, Ahmad-Reza Sadeghi:
It's hammer time: how to attack (rowhammer-based) DRAM-PUFs. 65:1-65:6 - Younghyun Kim
CamPUF: physically unclonable function based on CMOS image sensor fixed pattern noise. 66:1-66:6 - Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty
Tamper-resistant pin-constrained digital microfluidic biochips. 67:1-67:6 - Anil Kanduri, Antonio Miele
Approximation-aware coordinated power/performance management for heterogeneous multi-cores. 68:1-68:6 - Anuj Pathania
QoS-aware stochastic power management for many-cores. 69:1-69:6 - Geraldo F. Oliveira, Larissa Rozales Gonçalves, Marcelo Brandalero
Employing classification-based algorithms for general-purpose approximate computing. 70:1-70:6 - Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu:
Using imprecise computing for improved non-preemptive real-time scheduling. 71:1-71:6 - Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. 72:1-72:6 - Michael Bedford Taylor:
Basejump STL: systemverilog needs a standard template library for hardware design. 73:1-73:6 - Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. 74:1-74:10 - Derong Liu, Zheng Zhao, Zheng Wang
OPERON: optical-electrical power-efficient route synthesis for on-chip signals. 75:1-75:6 - Subrahmanya Teja, Jaydeep P. Kulkarni:
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation. 76:1-76:6 - Amit Ranjan Trivedi, Ahish Shylendra:
Ultralow power acoustic feature-scoring using gaussian I-V transistors. 77:1-77:6 - Hyunsu Chae
Test cost reduction for X-value elimination by scan slice correlation analysis. 78:1-78:6 - Christian Dietrich
Cross-layer fault-space pruning for hardware-assisted fault injection. 79:1-79:6 - Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer:
A machine learning based hard fault recuperation model for approximate hardware accelerators. 80:1-80:6 - Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha:
SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. 81:1-81:6 - Mark Clark, Avinash Kodi, Razvan C. Bunescu, Ahmed Louri:
LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs. 82:1-82:6 - Rodrigo Cataldo, Ramon Fernandes, Kevin J. M. Martin
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications. 83:1-83:6 - Xianwei Cheng, Yang Zhao
Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs. 84:1-84:6 - Shivam Swami, Joydeep Rakshit, Kartik Mohanram:
STASH: security architecture for smart hybrid memories. 85:1-85:6 - Shivam Swami, Kartik Mohanram:
ACME: advanced counter mode encryption for secure non-volatile memories. 86:1-86:6 - Poovaiah M. Palangappa, Kartik Mohanram:
CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. 87:1-87:6 - Patrick Cronin, Chengmo Yang, Yongpan Liu:
A collaborative defense against wear out attacks in non-volatile processors. 88:1-88:6 - Sandip Ray, Wen Chen, Rosario Cammarota:
Protecting the supply chain for automotives and IoTs. 89:1-89:4 - Xavier Carpent
Reconciling remote attestation and safety-critical operation on simple IoT devices. 90:1-90:6 - Bo-Yuan Huang
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. 91:1-91:6 - Debjit Pal
Application level hardware tracing for scaling post-silicon debug. 92:1-92:6 - Haifeng Gu, Mingsong Chen, Tongquan Wei, Li Lei, Fei Xie:
Specification-driven automated conformance checking for virtual prototype and post-silicon designs. 93:1-93:6 - Perry van Wesel, Julien Schmaltz:
Formal micro-architectural analysis of on-chip ring networks. 94:1-94:6 - Hanbin Hu
HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuits. 95:1-95:6 - He-Teng Zhang
Cost-aware patch generation for multi-target function rectification of engineering change orders. 96:1-96:6 - Enrique Díaz, Enrico Mezzetti
Modelling multicore contention on the AURIXTM TC27x. 97:1-97:6 - David Trilla, Carles Hernández
Cache side-channel attacks and time-predictability in high-performance critical real-time systems. 98:1-98:6 - Mischa Möstl
Cross-layer dependency analysis with timing dependence graphs. 99:1-99:6 - Matina Maria Trompouki
Brook auto: high-level certification-friendly programming for GPU-powered automotive systems. 100:1-100:6 - Christine Jakobs
Dynamic vehicle software with AUTOCONT. 101:1-101:6 - Artur Mrowca, Thomas Pramsohler, Sebastian Steinhorst
Automated interpretation and reduction of in-vehicle network traces at a large scale. 102:1-102:6 - Ximing Qiao, Xiong Cao, Huanrui Yang, Linghao Song
Atomlayer: a universal reRAM-based CNN accelerator with atomic layer computation. 103:1-103:6 - Fuqiang Liu, Chenchen Liu:
Towards accurate and high-speed spiking neuromorphic systems with data quantization-aware deep networks. 104:1-104:6 - Shaahin Angizi, Zhezhi He, Adnan Siraj Rakin, Deliang Fan:
CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator. 105:1-105:6 - Peiqi Wang, Yu Ji, Chi Hong, Yongqiang Lyu, Dongsheng Wang, Yuan Xie:
SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory. 106:1-106:6 - Yi Cai, Yujun Lin
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification. 107:1-107:6 - Mohsen Imani, Chenyu Huang, Deqian Kong, Tajana Rosing:
Hierarchical hyperdimensional computing for energy efficient classification. 108:1-108:6 - Shiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao:
Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. 109:1-109:6 - Hayato Yamaki, Hiroaki Nishi
Data prediction for response flows in packet processing cache. 110:1-110:6 - Fabio Montagna, Abbas Rahimi
PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform. 111:1-111:6 - Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. 112:1-112:6 - Yang Song
SARA: self-aware resource allocation for heterogeneous MPSoCs. 113:1-113:6 - Chen Li, Andrew Zigerelli, Jun Yang, Yang Guo:
PEP: proactive checkpointing for efficient preemption on GPUs. 114:1-114:6 - Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min:
FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs. 115:1-115:6 - Wei-Lin Wang, Tseng-Yi Chen
Minimizing write amplification to enhance lifetime of large-page flash-memory storage devices. 116:1-116:6 - Kun-Cheng Hsu, Che-Wei Tsao, Yuan-Hao Chang
Proactive channel adjustment to improve polar code capability for flash storage devices. 117:1-117:6 - Chien-Chung Ho, Yung-Chun Li, Yuan-Hao Chang
Achieving defect-free multilevel 3D flash memories with one-shot program design. 118:1-118:6 - Jungmin Park, Xiaolin Xu, Yier Jin
Power-based side-channel instruction-level disassembler. 119:1-119:6 - Alessandro Barenghi
Side-channel security of superscalar CPUs: evaluating the impact of micro-architectural features. 120:1-120:6 - Yiwen Gao
Electro-magnetic analysis of GPU-based AES implementation. 121:1-121:6 - Abhishek Chakraborty, Yang Xie, Ankur Srivastava
GPU obfuscation: attack and defense strategies. 122:1-122:6 - Suzana Milutinovic, Jaume Abella
Measurement-based cache representativeness on multipath programs. 123:1-123:6 - Jian-Jun Han, Wen Cai, Dakai Zhu:
Resource-aware partitioned scheduling for heterogeneous multicore real-time systems. 124:1-124:6 - Maria A. Serrano, Eduardo Quiñones:
Response-time analysis of DAG tasks supporting heterogeneous computing. 125:1-125:6 - Han-Yi Lin, Chia-Chun Hung, Pi-Cheng Hsiu
Duet: an OLED & GPU co-management scheme for dynamic resolution adaptation. 126:1-126:6 - Shail Dave
RAMP: resource-aware mapping for CGRAs. 127:1-127:6 - S. Alexander Chin, Jason Helge Anderson:
An architecture-agnostic integer linear programming approach to CGRA mapping. 128:1-128:6 - Manupa Karunaratne, Cheng Tan
Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs. 129:1-129:6 - Samuel Rogers, Hamed Tabkhi:
Locality aware memory assignment and tiling. 130:1-130:6 - Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: mask optimization with lithography-guided generative adversarial nets. 131:1-131:6 - Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou:
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits. 132:1-132:6 - Ali Abbasinasab, Malgorzata Marek-Sadowska:
RAIN: a tool for reliability assessment of interconnect networks - physics to software. 133:1-133:6 - Xiao Shi, Fengyuan Liu, Jun Yang, Lei He:
A fast and robust failure analysis of memory circuits using adaptive importance sampling method. 134:1-134:6 - Liqiang Lu, Yun Liang:
SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAs. 135:1-135:6 - Athanasios Xygkis, Lazaros Papadopoulos, David Moloney, Dimitrios Soudris
Efficient winograd-based convolution kernel implementation on edge devices. 136:1-136:6 - Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu
An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. 137:1-137:6 - Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
Content addressable memory based binarized neural network accelerator using time-domain signal processing. 138:1-138:6 - Sumanta Chaudhuri
A security vulnerability analysis of SoCFPGA architectures. 139:1-139:6 - Satwik Patnaik
Raise your game for split manufacturing: restoring the true functionality through BEOL. 140:1-140:6 - Boyu Zhang, Jonathon Crandall Magaña, Azadeh Davoodi:
Analysis of security of split manufacturing using machine learning. 141:1-141:6 - Marjan Ghodrati, Bilgiday Yuce, Surabhi Gujar, Chinmay Deshpande, Leyla Nazhandali, Patrick Schaumont
Inducing local timing fault through EM injection. 142:1-142:6 - Zhicheng Fu, Zhao Wang, Chunhui Guo, Zhenyu Zhang, Shangping Ren, Lui Sha:
IAfinder: identifying potential implicit assumptions to facilitate validation in medical cyber-physical system. 143:1-143:6 - Mohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava
An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems. 144:1-144:6 - Mohammad Saber Golanbari, Mehdi Baradaran Tahoori:
Runtime adjustment of IoT system-on-chips for minimum energy operation. 145:1-145:6 - Burhan Ahmad Mudassar, Jong Hwan Ko, Saibal Mukhopadhyay:
Edge-cloud collaborative processing for intelligent internet of things: a case study on smart surveillance. 146:1-146:6 - Song Han, William J. Dally:
Bandwidth-efficient deep learning. 147:1-147:6 - Kiseok Kwon, Alon Amid
Co-design of deep neural nets and neural net accelerators for embedded vision applications. 148:1-148:6 - Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Generalized augmented lagrangian and its applications to VLSI global placement. 149:1-149:6 - Haocheng Li
Routability-driven and fence-aware legalization for mixed-cell-height circuits. 150:1-150:6 - Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. 151:1-151:6 - Zhuo Feng:
Similarity-aware spectral sparsification by edge filtering. 152:1-152:6 - Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong:
S2FA: an accelerator automation framework for heterogeneous computing in datacenters. 153:1-153:6 - Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang:
Automated accelerator generation and optimization with composable, parallel and pipeline architecture. 154:1-154:6 - Christian Pilato, Francesco Regazzoni
TAO: techniques for algorithm-level obfuscation during high-level synthesis. 155:1-155:6 - Juan Escobedo, Mingjie Lin:
Extracting data parallelism in non-stencil kernel computing by optimally coloring folded memory conflict graph. 156:1-156:6 - Salim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar:
SMApproxlib: library of FPGA-based approximate multipliers. 157:1-157:6 - Aidyn Zhakatayev, Sugil Lee, Hyeon Uk Sim, Jongeun Lee:
Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks. 158:1-158:6 - Salim Ullah
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. 159:1-159:6 - Marcelo Brandalero
Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications. 160:1-160:6 - Vahideh Akhlaghi, Sicun Gao, Rajesh K. Gupta:
LEMAX: learning-based energy consumption minimization in approximate computing with quality guarantee. 161:1-161:6 - Shaahin Angizi, Zhezhi He, Deliang Fan:
PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation. 162:1-162:6 - Tsun-Ming Tseng
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration. 163:1-163:6 - Chunfeng Liu, Bing Li, Tsung-Yi Ho
Design-for-testability for continuous-flow microfluidic biochips. 164:1-164:6 - Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, Sung Kyu Lim
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor. 165:1-165:6 - Kangjun Bai
Enabling a new era of brain-inspired computing: energy-efficient spiking neural network with ring topology. 166:1-166:6 - Bonan Yan, Xiong Cao, Hai (Helen) Li:
A neuromorphic design using chaotic mott memristor with relaxation oscillation. 167:1-167:6 - Quan Deng, Lei Jiang, Youtao Zhang, Minxuan Zhang, Jun Yang:
DrAcc: a DRAM based accelerator for accurate CNN inference. 168:1-168:6 - Marco Donato, Brandon Reagen, Lillian Pentecost
On-chip deep neural network storage with multi-level eNVM. 169:1-169:6 - Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. 170:1-170:6 - Anup Das
VRL-DRAM: improving DRAM performance via variable refresh latency. 171:1-171:6 - Shuo-Han Chen
Enabling union page cache to boost file access performance of NVRAM-based storage device. 172:1-172:6 - Haibo Zhang, Prasanna Venkatesh Rengasamy, Nachiappan Chidambaram Nachiappan, Shulin Zhao, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das:
FLOSS: FLOw sensitive scheduling on mobile platforms. 173:1-173:6 - Hyeonseok Jung
Context-aware dataflow adaptation technique for low-power multi-core embedded systems. 174:1-174:6 - Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß
Architecture decomposition in system synthesis of heterogeneous many-core systems. 175:1-175:6 - Jintaek Kang, Kwanghyun Chung, Youngmin Yi, Soonhoi Ha:
NNsim: fast performance estimation based on sampled simulation of GPGPU kernels for neural networks. 176:1-176:6 - Ujjwal Gupta, Manoj Babu, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Ümit Y. Ogras
STAFF: online learning with stabilized adaptive forgetting factor and feature selection algorithm. 177:1-177:6 - Felipe da Rosa, Vitor V. Bandeira, Ricardo Reis
Extensive evaluation of programming models and ISAs impact on multicore soft error reliability. 178:1-178:6 - Dmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Optimized selection of wireless network topologies and components via efficient pruning of feasible paths. 179:1-179:6
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