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23. FPGA 2015: Monterey, CA, USA
- George A. Constantinides, Deming Chen:
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015. ACM 2015, ISBN 978-1-4503-3315-3
Designer's Day Session 1
- Ephrem Wu
, Inkeun Cho:
Physical Design Space Exploration. 1-4 - Joshua S. Monson, Brad L. Hutchings:
Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs. 5-8
Designer's Day Session 2
- Deshanand P. Singh
High-Level Design Tools for Floating Point FPGAs. 9-12 - Myron King, Jamey Hicks, John Ankcorn:
Software-Driven Hardware Development. 13-22 - Nachiket Kapre, Harnhua Ng, Kirvy Teo, Jaco Naude:
InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters. 23-26
Designer's Day Session 3
- Fernando Martinez-Vallina, Henry Styles:
Unlocking FPGAs Using High Level Synthesis Compiler Technologies. 27 - Keerthan Jaic, Melissa C. Smith:
Enhancing Hardware Design Flows with MyHDL. 28-31 - James Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy
Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow. 32-35
Keynote Speech
- Chen Chang:
The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 Years. 36
Technical Session 1: Computer-aided Design
- Evan Wegley, Qinhai Zhang:
Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs. 37-45 - Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. 46-55 - Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. 56-65 - Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings:
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. 66-69 - Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene:
Technology Mapping into General Programmable Cells. 70-73
Technical Session 2: Configuration and Processing
- Xinyu Niu, Wayne Luk, Yu Wang:
EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access. 74-83 - Yu Bai, Mingjie Lin:
Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs). 84-93 - Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. 94-97
Technical Session 3: Architecture 1
- Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz:
Take the Highway: Design for Embedded NoCs on FPGAs. 98-107 - Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer:
Enhancements in UltraScale CLB Architecture. 108-116 - Martin Langhammer, Bogdan Pasca
Floating-Point DSP Block Architecture for FPGAs. 117-125
Technical Session 4: Architecture 2: Memory Systems
- Joseph G. Wingbermuehle, Ron K. Cytron
Superoptimized Memory Subsystems for Streaming Applications. 126-135 - Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides:
MATCHUP: Memory Abstractions for Heap Manipulating Programs. 136-145 - Edin Kadric
Impact of Memory Architecture on FPGA Energy Consumption. 146-155 - Eric Matthews, Nicholas C. Doyle, Lesley Shannon:
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems. 156-159
Evening Panel
- John Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig:
Growing a Healthy FPGA Ecosystem. 160
Technical Session 5: Processors and Accelerators
- Chen Zhang
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. 161-170 - Aaron Severance, Joe Edwards, Guy G. F. Lemieux:
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. 171-180 - Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre:
On Data Forwarding in Deeply Pipelined Soft Processors. 181-189
Technical Session 6: High-level and System-level Synthesis
- Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. 190-199 - Peng Li
Resource-Aware Throughput Optimization for High-Level Synthesis. 200-209 - Xitong Gao
Numerical Program Optimization for High-Level Synthesis. 210-213 - Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica:
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. 214-217
Technical Session 7: Circuit Design
- Dmitry Burlyaev, Pascal Fradet, Alain Girault:
Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits. 218-227 - Harald Homulle
200 MS/s ADC implemented in a FPGA employing TDCs. 228-235 - Makoto Miyamura, Toshitsugu Sakamoto, Yukihide Tsuji
0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL. 236-239
Technical Session 8: Applications
- Ren Chen, Sruja Siriyal, Viktor K. Prasanna:
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA. 240-249 - James Arram, Wayne Luk, Peiyong Jiang:
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment. 250-259
Poster Session 1
- Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink:
An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only). 261 - Alban Bourge, Olivier Muller, Frédéric Rousseau:
A Novel Method for Enabling FPGA Context-Switch (Abstract Only). 261 - Wentai Zhang, Li Shen, Thomas Page, Guojie Luo, Peng Li
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). 261 - Elias Vansteenkiste, Berg Severens, Dirk Stroobandt:
Logic Gates in the routing network of FPGAs (Abstract Only). 262 - Martinianos Papadopoulos, Christos Ttofis, Christos Kyrkou, Theocharis Theocharides:
Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only). 262 - Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). 262 - Michaela E. Amoo, Youngsoo Kim, Vance Alford, Shrikant Jadhav
An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only). 263 - Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura:
Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only). 263 - Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei:
Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). 263 - Navid Rahmanikia
Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only). 264 - Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab:
Formal Verification ATPG Search Engine Emulator (Abstract Only). 264 - Ralf Salomon, Ralf Joost, Matthias Hinkfoth:
Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only). 265
Poster Session 2
- Yutaro Ishigaki
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). 266 - Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). 266 - Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache:
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). 266 - Leibo Liu, Yingjie Victor Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei:
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). 267 - Charles Mutigwe, Johnson Kinyua, Farhad Aghdasi:
FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only). 267 - Naoto Nojiri, Lin Meng
FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only). 267 - Ryota Takasu, Yoichi Tomioka, Takashi Aoki, Hitoshi Kitazawa:
An FPGA Implementation of Multi-stream Tracking Hardware using 2D SIMD Array (Abstract Only). 268 - Lei Chen, Yuanfu Zhao, Zhiping Wen, Jing Zhou, Xuewu Li, Yanlong Zhang, Huabo Sun:
300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only). 268 - Bo Wang, Leibo Liu:
REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only). 269 - Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada:
Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only). 269 - Xianjian Zheng, Fan Zhang, Lei Chen, Zhiping Wen, Yuanfu Zhao, Xuewu Li:
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only). 269 - Junbin Wang, Leibo Liu
A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). 270
Poster Session 3
- Youngsoo Kim, William Harding, Clay S. Gloster Jr., Winser E. Alexander:
Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only). 271 - Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang, Haojie Zhou:
An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only). 271 - Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar:
FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only). 271 - Mohammed Alawad, Mingjie Lin:
Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only). 272 - Tomasz S. Czajkowski:
Silicon Verification using High-Level Design Tools (Abstract Only). 272 - Gerardo Soria García, Adrian Pedroza de-la-Crúz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano:
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only). 272 - Sanmukh R. Kuppannagari, Viktor K. Prasanna:
Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only). 273 - Zhuo Qian, Martin Margala:
A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only). 273 - Chao Wang, Xi Li, Qi Guo, Xuehai Zhou:
RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only). 273 - Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti:
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). 274 - Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets:
Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only). 274
Poster Session 4
- Amir Momeni, Hamed Tabkhi, Gunar Schirner, David R. Kaeli:
Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only). 275 - Hongyuan Ding, Miaoqing Huang:
An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only). 275 - Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar:
MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only). 275 - Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He:
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). 276 - Danyal Mohammadi
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only). 276 - Shao Lin S. T. Tang, Guy Lemieux:
Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only). 276 - Jie Wang, Jason Cong:
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). 276 - Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Osman S. Unsal, Adrián Cristal
Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only). 277 - Siddhartha, Nachiket Kapre:
FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only). 277 - Masahiro Fujita:
On Implementation of LUT with Large Numbers of Inputs (Abstract Only). 277 - Seung Yeol Baik, Seokjin Jeong, Hyeong-Cheol Oh:
Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only). 278
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