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ISSCC 2020: San Francisco, CA, USA
- 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. IEEE 2020, ISBN 978-1-7281-3205-1
- Sensen Li, Taiyun Chi, Doohwan Jung, Tzu-Yuan Huang, Min-Yu Huang, Hua Wang
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4.2 An E-Band High-Linearity Antenna-LNA Front-End with 4.8dB NF and 2.2dBm IIP3 Exploiting Multi-Feed On-Antenna Noise-Canceling and Gm-Boosting. 1-3 - Moon Hyung Jang
9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. 1-3 - Jeffrey Dean:
1.1 The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design. 8-14 - Kou-Hung Lawrence Loh:
1.2 Fertilizing AIoT from Roots to Leaves. 15-21 - Nadine Collaert
1.3 Future Scaling: Where Systems and Technology Meet. 25-29 - Dario Gil, William M. J. Green:
1.4 The Future of Computing: Bits + Neurons + Qubits. 30-39 - Teja Singh, Sundar Rangarajan, Deepesh John, Russell Schreiber, Spence Oliver, Rajit Seahra, Alex Schaefer:
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core. 42-44 - Samuel Naffziger, Kevin Lepak, Milam Paraschou, Mahesh Subramony:
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 44-45 - Pascal Vivet
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. 46-48 - Young-Duk Kim, Wookyeong Jeong, Lakkyung Jung, Dongsuk Shin, Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong:
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU. 48-50 - Hugh Mair, Ericbill Wang, Ashish Nayak, Rolf Lagerquist, Loda Chou, Gordon Gammie, HsinChen Chen, Lee-Kee Yong, Manzur Rahman, Jenny Wiedemeier, Ramu Madhavaram, Alex Chiou, Blundt Li, Vincent Lin, Rory Huang, Michael Yanq, Achuta Thippana, Osric Su, S. A. Huang:
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC. 50-52 - Rama Venkatasubramanian, Don Steiss, Greg Shurtz, Tim Anderson, Kai Chirca, Raghavendra Santhanagopal, Niraj Nandan, Anish Reghunath, Hetul Sanghvi, Daniel Wu, Abhijeet Chachad, Brian Karguth, Denis Beaudoin, Charles Fuoco, Lewis Nardini, Chunhua Hu, Sam Visalli, Amrit Mundra, Devanathan Varadarajan, Frank Cano, Shane Stelmach, Mihir Mody, Arthur Redfern, Haydar Bilhan, Maher Sarraj, Ali Siddiki, Anthony Lell, Eldad Falik, Anthony M. Hill, Abhinay Armstrong, Todd Beck, Vijay Kanumuri, Steven Mullinnix, Darnell Moore, Jason Jones, Manoj Koul, Sanjive Agarwala:
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. 52-54 - Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Pradeep Parashurama, Ramon Bertran
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor. 54-56 - Danielle Griffith
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production. 58-60 - Amr Khashaba, Junheng Zhu, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
3.2 A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92fJ·K2 FoM in 65nm CMOS. 60-62 - Li Xu
3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection. 62-64 - Çagri Gürleyük, Sining Pan, Kofi A. A. Makinwa:
3.4 A 16MHz CMOS RC Frequency Reference with ±400ppm Inaccuracy from -45°C to 85°C After Digital Linear Temperature Compensation. 64-66 - Amr Khashaba, Junheng Zhu, Mostafa Gamal Ahmed, Nilanjan Pal, Pavan Kumar Hanumolu:
3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors. 66-68 - Sining Pan, Kofi A. A. Makinwa:
3.6 A CMOS Resistor-Based Temperature Sensor with a 10fJ·K2 Resolution FoM and 0.4°C (30) Inaccuracy From -55°C to 125°C After a 1-point Trim. 68-70 - Saleh Heidary Shalmany, Kamran Souri, Uaur Sonmez, Kianoush Souri, Michele D'Urbino, Said Hussaini, Darryl Tauro, Sassan Tabatabaei:
3.7 A 620µW BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190fJ·K2. 70-72 - Chenu-Hsing Liao, Shang-Hsien Yang, Meng-Yin Liao, Kai-Cheng Chung, Neha Kumari, Ke-Horng Chen
3.8 A 23.6ppm/°C Monolithically Integrated GaN Reference Voltage Design with Temperature Range from -50°C to 200°C and Supply Voltage Range from 3.9 to 24V. 72-74 - Hyun-Chul Park, D. Kang, S. M. Lee, B. Park, K. Kim, Jooseok Lee, Y. Aoki, Y. Yoon, S. Lee, D. Lee, D. Kwon, Seokhyeon Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, Donggyu Minn, I. Park, S. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Cho, S. T. Choi, K. H. An, Y. Kim, J. H. Lee, Jae-Ick Son, Sung-Gi Yang:
4.1 A 39GHz-Band CMOS 16-Channel Phased-Array Transceiver IC with a Companion Dual-Stream IF Transceiver IC for 5G NR Base-Station Applications. 76-78 - Robin Garg
4.3 A 28GHz 4-Element MIMO Beam-Space Array in 65nm CMOS with Simultaneous Spatial Filtering and Single-Wire Frequency-Domain Multiplexing. 80-82 - Susnata Mondal
4.4 A 28/37GHz Scalable, Reconfigurable Multi-Layer Hybrid/Digital MIMO Transceiver for TDD/FDD and Full-Duplex Communication. 82-84 - Anandaroop Chakrabarti, Chintan Thakkar, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance. 84-86 - Xuyang Lu, Suresh Venkatesh
4.6 Space-Time Modulated 71-to-76GHz mm-Wave Transmitter Array for Physically Secure Directional Wireless Links. 86-88 - Milad Kalantari, Hossein Shirinabadi, Ali Fotowat-Ahmadi, C. Patrick Yue:
4.7 A Single-Antenna W-Band FMCW Radar Front-End Utilizing Adaptive Leakage Cancellation. 88-90 - Xiang Yi, Cheng Wang, Muting Lu, Jinchen Wang, Jesús Grajal, Ruonan Han:
4.8 A Terahertz FMCW Comb Radar in 65nm CMOS with 100GHz Bandwidth. 90-92 - Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE. 94-96 - Toru Okino, Shota Yamada, Yusuke Sakata, Shigetaka Kasuga, Masato Takemoto, Yugo Nose, Hiroshi Koshida, Masaki Tamaru, Yuki Sugiura, Shigeru Saito, Shinzo Koyama, Mitsuyoshi Mori, Yutaka Hirose, Masayuki Sawada, Akihiro Odagawa, Tsuyoshi Tanaka:
5.2 A 1200×900 6µm 450fps Geiger-Mode Vertical Avalanche Photodiodes CMOS Image Sensor for a 250m Time-of-Flight Ranging System Using Direct-Indirect-Mixed Frame Synthesis with Configurable-Depth-Resolution Down to 10cm. 96-98 - C.-L. Chen, S.-W. Chu, B.-J. Chen, Y.-F. Lyu, Kai-Chi Hsu, C.-F. Liang, S.-S. Su, M.-J. Yang, C.-Y. Chen, S.-L. Cheng, H.-D. Liu, C.-T. Lin, K. P. Petrov, H.-W. Chen, K.-C. Chu, P.-C. Wu, P.-T. Huang, Neil Na
5.3 An Up-to-1400nm 500MHz Demodulated Time-of-Flight Image Sensor on a Ge-on-Si Platform. 98-100 - Donguk Kim, Seunghyun Lee, Dahwan Park, Canxing Piao, Jihoon Park, Yeonsoo Ahn, Kihwan Cho, Jungsoon Shin, Seung Min Song, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi:
5.4 A Dynamic Pseudo 4-Tap CMOS Time-of-Flight Image Sensor with Motion Artifact Suppression and Background Light Cancelling Over 120klux. 100-102 - Jaekyu Lee, Seung Sik Kim, In-Gyu Baek, Heesung Shim, Taehoon Kim, Taehyoung Kim, Jungchan Kyoung, Dongmo Im, Jinyong Choi, KeunYeong Cho, Daehoon Kim, Haemin Lim, Min-Woong Seo, JuYoung Kim, Doowon Kwon, Jiyoun Song, Jiyoon Kim, Minho Jang, Joosung Moon, Hyunchul Kim, Chong Kwang Chang, JinGyun Kim, Kyoungmin Koh, Hanjin Lim, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang:
5.5 A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology. 102-104 - Hyunchul Kim, Jongeun Park, Insung Joe, Doowon Kwon, Joo Hyoung Kim, Dongsuk Cho, Taehun Lee, Changkyu Lee, Haeyong Park, Soojin Hong, Chongkwang Chang, Jingyun Kim, Hanjin Lim, Youngsun Oh, Yitae Kim, Seungjoo Nah, Sangil Jung, Jaekyu Lee, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang:
5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology. 104-106 - Yorito Sakano, Takahiro Toyoshima, Ryosuke Nakamura, Tomohiko Asatsuma, Yuki Hattori, Takayuki Yamanaka, Ryoichi Yoshikawa, Naoki Kawazu, Tomohiro Matsuura, Takahiro Iinuma, Takahiro Toya, Tomohiko Watanabe, Atsushi Suzuki, Yuichi Motohashi, Junichiro Azami, Yasushi Tateshita, Tsutomu Haruta:
5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance. 106-108 - Mamoru Sato, Yuhi Yorikado, Yusuke Matsumura, Hideki Naganuma, Eriko Kato, Takuya Toyofuku, Akihiko Kato, Yusuke Oike:
5.8 A 0.50e-rmsNoise 1.45µm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps. 108-110 - Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh:
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. 110-112 - Thomas Finateu, Atsumi Niwa, Daniel Matolin, Koya Tsuchimoto, Andrea Mascheroni, Etienne Reynaud, Pooria Mostafalu, Frederick T. Brady, Ludovic Chotard, Florian Le Goff, Hirotsugu Takahashi, Hayato Wakabayashi, Yusuke Oike, Christoph Posch
5.10 A 1280×720 Back-Illuminated Stacked Temporal Contrast Event-Based Vision Sensor with 4.86µm Pixels, 1.066GEPS Readout, Programmable Event-Rate Controller and Compressive Data-Formatting Pipeline. 112-114 - Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. 116-118 - Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung:
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. 118-120 - Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai:
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET. 120-122 - Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin:
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. 122-124 - Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. 124-126 - Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. 126-128 - Han-Gon Ko, Soyeong Shin
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. 128-130 - Pen-Jui Peng
6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS. 130-132 - Chien-Hung Lin, Chih-Chung Cheng, Yi-Min Tsai, Sheng-Je Hung, Yu-Ting Kuo, Perry H. Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, Shao-Yu Wang, Chin-Hua Kuo, Chih-Yu Chang, Ming-Hsien Lee, Tsung-Yao Lin, Chih-Cheng Chen:
7.1 A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC. 134-136 - Yang Jiao, Liang Han, Rong Jin, Yi-Jung Su, Chiente Ho, Li Yin, Yun Li, Long Chen, Zhen Chen, Lu Liu, Zhuyu He, Yu Yan, Jun He, Jun Mao, Xiaotao Zai, Xuejun Wu, Yongquan Zhou, Mingqiu Gu, Guocai Zhu, Rong Zhong, Wenyuan Lee, Ping Chen, Yiping Chen, Weiliang Li, Deyu Xiao, Qing Yan, Mingyuan Zhuang, Jiejun Chen, Yun Tian, Yingzi Lin, Wei Wu, Hao Li, Zesheng Dou:
7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS. 136-140 - Kasho Yamamoto, Kota Ando, Normann Mertig
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. 138-140 - Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo:
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation. 140-142 - Wilfred Gomes, Sanjeev Khushu, Doug B. Ingerly, Patrick N. Stover, Nasirul I. Chowdhury, Frank O'Mahony, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Lei Jiang, Surya Prekke, Biswajit Patra, Pavel V. Rott, Rajesh Kumar:
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. 144-146 - Prasun K. Raha, Tomai Knopp, Sagheer Ahmad, Ahmad Ansari, Fu-Hing Ho, Thomas To, Vamsi Nalluri, Mrinal Sarmah, Rajeev Patwari:
8.2 A Versatile 7nm Adaptive Compute Acceleration Platform Processor. 146-148 - Robert Christy, Stuart Riches, Sujil Kottekkat, Prasanth Gopinath, Ketan Sawant, Anitha Kona, Rob Harrison:
8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications. 148-150 - Sal Dasgupta, Teja Singh, Ashish Jain, Samuel Naffziger, Deepesh John, Chetan Bisht, Pradeep Jayaraman:
8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. 150-152 - Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh:
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. 154-156 - Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun:
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. 158-160 - Lu Jie
9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. 160-162 - Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. 162-164 - Yan Song, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. 164-166 - Mitsuya Fukazawa, Takashi Oshima
9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS. 166-168 - Robert H. M. van Veldhoven, Marco Lammers, Leon van der Dussen, Khalid Mabtoul:
9.8 A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems. 168-170 - Gengzhen Qi, Haijun Shao, Pui-In Mak
10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. 172-174 - Shiyu Su, Mike Shuo-Wei Chen:
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. 174-176 - Ming-Da Tsai, Song-Yu Yang, Chi-Yao Yu, Ping-Yu Chen, Tzung-Han Wu, Mohammed Hassan, Chi-Tsan Chen, Chao-Wei Wang, Yen-Chuan Huang, Li-Han Hung, Wei-Hao Chiu, Anson Lin, Bo-Yu Lin, Arnaud Werquin, Chien-Cheng Lin, Yen-Horng Chen, Jen-Che Tsai, Yuan-Yu Fu, Bernard Tenbroek, Chinq-Shiun Chiu, Yi-Bin Lee, Guang-Kaai Dehng:
10.3 A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO. 176-178 - Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS. 178-180 - Assaf Ben Bassat, Shahar Gross, Anna Nazimov, Ashoke Ravi, Bassam Khamaisi, Elan Banin, Eli Borokhovich, Nahum Kimiagarov, Phillip Skliar, Rotem Banin, Sarit Zur, Sebastian Reinhold, Smadar Bruker, Tzvi Maimon, Uri Parker, Ofir Degani:
10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications. 180-182 - Ming-Da Tsai, Chien-Wei Tseng, Kuen-Jou Tsai, Shuja Andrabi, Pin-Cheng Huang, Federico Beffa, Yangjian Chen, Bernard Tenbroek:
10.6 A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection. 182-184 - Si-Wook Yoo, Shih-Chang Hung, Jeffrey S. Walling
10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS. 184-186 - Erfan Ghaderi, Chase Puglisi, Shrestha Bansal
10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS. 186-188 - Kang Wei, Yogesh Ramadass, Dongsheng Brian Ma:
11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation. 190-192 - Prescott H. McLaughlin, Ziyu Xia, Jason T. Stauth
11.2 A Fully Integrated Resonant Switched-Capacitor Converter with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator. 192-194 - Christoph Rindfleisch
11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency. 194-196 - Qi Cheng
11.4 A 48-to-80V Input 2MHz Adaptive ZVT-Assisted GaN-Based Bus Converter Achieving 14% Light-Load Efficiency Improvement. 196-198 - Mo Huang
11.5 A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5. 198-200 - Sung-Wan Hong:
11.6 A 1.46mm2 Simultaneous Energy-Transferring Single-Inductor Bipolar-Output Converter with a Flying Capacitor for Highly Efficient AMOLED Display in 0.5µm CMOS. 200-202 - Jongbeom Baek, Takahiro Nomiyama, Seungchan Park, Young-Ho Jung, Dongsu Kim, Jae-Yeol Han, Jun-Suk Bang, Yumi Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate. 202-204 - Min-Woo Ko, Gyeong-Gu Kang, Ki-Duk Kim, Ji-Hun Lee, Seok-Tae Koh, Tae-Hwang Kong, Sang-Ho Kim, Sungyong Lee, Michael Choi, Jongshin Shin, Gyu-Hyeong Cho, Hyunsik Kim:
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries. 204-206 - Hao Li, Ganesh Balamurugan, Meer Sakib, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper:
12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control. 208-210 - Enrico Sentieri, Tino Copani, Andrea Paganini, Matteo Traldi, Angelo Palladino, Antonio Santipo, Lorenzo Gerosa, Matteo Repossi, Gianluca Catrini, Marta Campo, Francesco Radice, Andrea Diodato, Roberto Pelleriti, Daniele Baldi, Laura Tarantini, Luca Maggi, Gianluca Radaelli, Stefano Cervini, Francesco Clerici, Angelo Moroni:
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications. 210-212 - Teruo Jyo, Munehiko Nagatani, Josuke Ozaki, Mitsuteru Ishikawa, Hideyuki Nosaka
12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters. 212-214 - Hannes Ramon, Michiel Verplaetse, Michael Vanhoecke, Haolin Li, Johan Bauwelinck
12.4 A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver. 214-216 - Doo-Hyun Kim, Hyunggon Kim, Sung-Won Yun, Youngsun Song, Jisu Kim, Sung-Min Joe, Kyung-Hwa Kang, Joonsuc Jang, Hyun-Jun Yoon, Kangbin Lee, Minseok Kim, Joonsoo Kwon, Jonghoo Jo, Sehwan Park, Jiyoon Park, Jisoo Cho, Sohyun Park, Garam Kim, Jinbae Bang, Heejin Kim, Jongeun Park, Deokwoo Lee, Seonyong Lee, Hwajun Jang, Hanjun Lee, Donghyun Shin, Jungmin Park, Jungkwan Kim, Jongmin Kim, Kichang Jang, II Han Park, Seung Hyun Moon, Myung-Hoon Choi, Pansuk Kwak, Joo-Yong Park, Youngdon Choi, Sanglok Kim, Seungjae Lee
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate. 218-220 - Hwang Huh, Wanik Cho, Jinhaeng Lee, Yujong Noh, Yongsoon Park, Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique. 220-221 - Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. 222-224 - Tung-Cheng Chang, Yen-Cheng Chiu, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Meng-Fan Chang:
13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices. 224-226 - Toshiyuki Kouchi, Noriyasu Kumazaki, Masashi Yamaoka, Sanad Bushnaq, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Akio Sugahara, Akihiro Imamoto, Norichika Asaoka, Ryosuke Isomura, Takaya Handa, Junichi Sato, Hiromitsu Komai, Atsushi Okuyama, Naoaki Kanagawa, Yasufumi Kajiyama, Yuri Terada, Hidekazu Ohnishi, Hiroki Yabe, Cynthia Hsu, Mami Kakoi, Masahiro Yoshihara:
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs. 226-228 - Weiwei Shan, Minhao Yang, Jiaming Xu, Yicheng Lu, Shuai Zhang, Tao Wang, Jun Yang, Longxing Shi, Mingoo Seok:
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. 230-232 - Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. 232-234 - Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. 234-236 - Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. 238-240 - Jian-Wei Su
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. 240-242 - Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. 242-244 - Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. 244-246 - Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. 246-248 - Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett:
16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. 250-252 - Minglei Zhang
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. 252-254 - Zihao Zheng, Lai Wei, Jorge Lagos
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. 254-256 - Tsung-Chih Hung, Jia-Ching Wang, Tai-Haur Kuo:
16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme. 256-258 - Hooman Saeidi, Suresh Venkatesh
29.9 A 4×4 Distributed Multi-Layer Oscillator Network for Harmonic Injection and THz Beamforming with 14dBm EIRP at 416GHz in a Lensless 65nm CMOS IC. 256-258 - Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun:
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. 258-260 - Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. 260-262 - Tzu-Fan Wu, Mike Shuo-Wei Chen:
16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS. 262-264 - Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi:
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. 266-268 - Alessio Santiccioli, Mario Mercandelli
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. 268-270 - Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. 270-272 - Yiyang Shu, Huizhen Jenny Qian, Xun Luo:
17.4 A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting. 272-274 - Mario Mercandelli
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. 274-276 - Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton:
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS. 276-278 - Yizhe Hu, Xi Chen
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. 276-278 - Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. 278-280 - Younghyun Lim
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. 280-282 - Chao Fan
17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA. 282-284 - Yuanqing Huang, Yingping Chen, Dongsheng Brian Ma:
18.1 A Self-Health-Learning GaN Power Converter Using On-Die Logarithm-Based Analog SGD Supervised Learning and Online Tj-Independent Precursor Measurement. 286-288 - Maik Kaufmann
18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency. 288-290 - Yogesh Ramadass, Andrés Blanco, Boqiang Xiao, John Cummings:
18.3 A 120mA Non-Isolated Capacitor-Drop AC/DC Power Supply. 290-292 - Lisong Li, Xiangming Fang, Rongxiang Wu:
18.4 An 11MHz Fully Integrated 5kV Isolated DC-DC Converter Without Cross-Isolation-Barrier Feedback. 292-294 - Wei-Hsu Chang, Kun-Yu Lin, Chun-Ching Lee, Li-Di Lo, Jenn-Yu Lin, Ta-Yung Yang:
18.5 ZVS Flyback-Converter ICs Optimizing USB Power Delivery for Fast-Charging Mobile Devices to Achieve 93.5% Efficiency. 294-296 - Minho Choi, Deog-Kyoon Jeong:
18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor. 296-298 - Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka:
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. 298-300 - Hiroaki Ishihara, Kohei Onizuka:
18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK. 300-302 - Bishnu Patra
19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers. 304-306 - Loïck Le Guevel
19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot. 306-308 - Jiang Gong, Yue Chen
19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications. 308-310 - Po-Han Peter Wang
20.1 A 28µW IoT Tag That Can Communicate with Commodity WiFi Transceivers via a Single-Side-Band QPSK Backscatter Communication Technique. 312-314 - Zhixuan Wang
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. 314-316 - Si Hoon Lee, Kwangmin Park, Jaeheung Lim, Minchul Lee, Jeongho Park, Hyun Kim, Young Ok Lee, Hyun Su Ahn, Eunseok Shin, Hyungjong Ko, Seoung-Jae Yoo, Hyunsurk Ryu, Yongin Park, Joonseok Kim, Long Yan:
20.3 A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with Embedded 4×Gas Sensors, a Temperature Sensor and a Relative Humidity Sensor. 316-318 - Saransh Sharma
20.4 3D Surgical Alignment with 100µm Resolution Using Magnetic-Field Gradient-Based Localization. 318-320 - Yi-Chung Wu
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. 322-324 - Chieh Chung, Chia-Hsiang Yang:
21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots. 324-326 - Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chang-Hung Tsai, Ying-Jui Chen, Tung-Hsing Wu, Hue-Min Lin, Han-Liang Chou, Abrams Chen, Andy-HB Wang, W. C. Gu, Wayne Hsieh, Jing-Ying Chang, Shou-Chun Liao, Chen-Tsai Ho, Larry Chu, Sokonisa Wei, Chi-Hui Wang, Kevin Jou:
21.3 A 5.69mm2 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications. 326-328 - Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, Seungseob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee:
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. 330-332 - Dong-Uk Lee, Ho Sung Cho, Jihwan Kim, Young Jun Ku, Sangmuk Oh, Chul Dae Kim, Hyun Woo Kim, Wooyoung Lee, Tae-Kyun Kim, Tae Sik Yun, Min Jeong Kim, SeungGyeon Lim, Seong Hee Lee, Byung Kuk Yun, Jun Il Moon, Ji Hwan Park, Seokwoo Choi, Young Jun Park, Chang Kwon Lee, Chunseok Jeong, Jae-Seung Lee, Sang Hun Lee, Woo Sung We, Jong Chan Yun, Doobock Lee, Junghyun Shin, Seungchan Kim, Junghwan Lee, Jiho Choi, Yucheon Ju, Myeong-Jae Park, Kang Seol Lee, Youngdo Hur, Daeyong Shim, Sangkwon Lee, Junhyun Chun, Kyowon Jin:
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. 334-336 - Po-Wei Chiu, Chris H. Kim:
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. 336-338 - Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park:
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. 338-340 - Soyeong Shin
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. 340-342 - Mahdi Kashmiri, Behnam Behroozpour, Vladimir P. Petkov, Ken Wojciechowski, Christoph Lang:
23.1 A 4GS/s 80dB DR Current-Domain Analog Front-End for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive LiDAR. 344-346 - Yuxuan Luo, Yida Li
23.2 A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. 346-348 - Caspar P. L. van Vroonhoven:
23.3 A 0-to-60V-Input VCM Coulomb Counter with Signal-Dependent Supply Current and ±0.5% Gain Inaccuracy from -50°C to 125°C. 348-350 - Shoubhik Karmakar, Huajun Zhang
23.4 A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission. 350-352 - Shih-Hsiung Chien, Tai-Haur Kuo, Hung-Yi Huang, Hong-Bin Wang, Yi-Zhi Qiu
23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction. 352-354 - Eunchul Kang, Mingliang Tan
23.6 A 2pA/√Hz Transimpedance Amplifier for Miniature Ultrasound Probes with 36dB Continuous-Time Gain Compensation. 354-356 - Sanfeng Zhang
23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication. 356-358 - Yunhong Kim, Sungsik Park, Seung-Woo Song, Sangwoo Lee
23.8 A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation. 358-360 - Fei Wang, Hua Wang
24.1 A 24-to-30GHz Watt-Level Broadband Linear Doherty Power Amplifier with Multi-Primary Distributed-Active-Transformer Power-Combining Supporting 5G NR FR2 64-QAM with >19dBm Average Pout and >19% Average PAE. 362-364 - Mannem Naga Sasikanth, Min-Yu Huang, Tzu-Yuan Huang, Sensen Li, Hua Wang
24.2 A Reconfigurable Series/Parallel Quadrature-Coupler-Based Doherty PA in CMOS SOI with VSWR Resilient Linearity and Back-Off PAE for 5G MIMO Arrays. 364-366 - Sensen Li, Min-Yu Huang, Doohwan Jung, Tzu-Yuan Huang, Hua Wang
24.3 A 28GHz Current-Mode Inverse-Outphasing Transmitter Achieving 40%/31% PA Efficiency at Psat/6dB PBO and Supporting 15Gbit/s 64-QAM for 5G Communication. 366-368 - Si-Wook Yoo, Shih-Chang Hung, Sang-Min Yoo:
24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique. 368-370 - Diyang Zheng, Yun Yin, Yiting Zhu, Liang Xiong, Yicheng Li, Na Yan, Hongtao Xu:
24.5 A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement. 370-372 - Fei Wang, Hua Wang
24.6 An Instantaneously Broadband Ultra-Compact Highly Linear PA with Compensated Distributed-Balun Output Network Achieving >17.8dBm P1dB and >36.6% PAEP1dB over 24 to 40GHz and Continuously Supporting 64-/256-QAM 5G NR Signals over 24 to 42GHz. 372-374 - Bart Philippe, Patrick Reynaert:
24.7 A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS. 374-376 - Weibo Wang, Fangjin Guo, Tangsheng Chen, Keping Wang:
24.8 A W-Band Power Amplifier with Distributed Common-Source GaN HEMT and 4-Way Wilkinson-Lange Combiner Achieving 6W Output Power and 18% PAE at 95GHz. 376-378 - Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. 380-382 - Jonghyun Oh
25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density. 382-384 - Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. 382-384 - Yan He, Kaiyuan Yang
25.3 A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance. 384-386 - Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li
25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing. 386-388 - Hsiu-Hsien Ting, Tai-Cheng Lee:
25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique. 390-392 - Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. 392-394 - Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok:
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. 394-396 - Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. 396-398 - Yun-Shiang Shu, Zhi-Xin Chen, Yu-Hong Lin, Su-Hao Wu, Wei-Hsiang Huang, Albert Yen-Chih Chiou, Chang-Yang Huang, Hung-Yi Hsieh, Fan-Wei Liao, Teng-Feng Zou, Ping Chen:
26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices. 400-402 - Gerard O'Leary, Jianxiong Xu, Liam Long, José B. Sales Filho
26.2 A Neuromorphic Multiplier-Less Bit-Serial Weight-Memory-Optimized 1024-Tree Brain-State Classifier and Neuromodulation SoC with an 8-Channel Noise-Shaping SAR ADC Array. 402-404 - Jun-Chau Chien, Hyongsok Tom Soh, Amin Arbabian:
26.4 A Cell-Capacitance-Insensitive CMOS Sample-and-Hold Chronoamperometric Sensor for Real-Time Measurement of Small Molecule Drugs in Whole Blood. 406-408 - Yuwei Wang, Quan Sun, Hongrui Luo, Xinlei Chen, Xiaofei Wang, Hong Zhang:
26.3 A Closed-Loop Neuromodulation Chipset with 2-Level Classification Achieving 1.5Vpp CM Interference Tolerance, 35dB Stimulation Artifact Rejection in 0.5ms and 97.8% Sensitivity Seizure Detection. 406-408 - Soumya Bose, Boyu Shen
26.5 A 20µW Heartbeat Detection System-on-Chip Powered by Human Body Heat for Self-Sustaining Wearable Healthcare. 408-410 - Changuk Lee, Taejune Jeon, Moon Hyung Jang
26.6 A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-Input and 300mVpp Linear Input Range for Closed-Loop Neural Recording. 410-412 - Fatemeh Marefat, Reza Erfani, Kevin L. Kilgore, Pedram Mohseni:
26.7 A 280µW 108dB DR Readout IC with Wireless Capacitive Powering Using a Dual-Output Regulating Rectifier for Implantable PPG Recording. 412-414 - Yaoyao Jia, Ulkuhan Guler
26.8 A Trimodal Wireless Implantable Neural Interface System-on-Chip. 414-416 - Jongyup Lim, Eunseong Moon, Michael Barrow, Samuel R. Nason, Paras R. Patel, Parag G. Patil, Sechang Oh, Inhee Lee
26.9 A 0.19×0.17mm2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry. 416-418 - Jonathan K. Brown, David Abdallah, Jim Boley, Nicholas Collins, Kyle Craig, Greg Glennon, Kuo-Ken Huang, Christopher J. Lukas
27.1 A 65nm Energy-Harvesting ULP SoC with 256kB Cortex-M0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System. 420-422 - Pranay Prabhat, Benoît Labbé
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power. 422-424 - Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. 424-426 - Yunhyeok Choi, Bohdan Karpinskyy, Kyoung-Moon Ahn, Yongsoo Kim, Soonkwan Kwon, Jieun Park, Yongki Lee, Mijung Noh:
27.4 Physically Unclonable Function in 28nm FD801 Technology Achieving High Reliability for AEC-Q100 Grade 1 and 1SO26262 ASIL-B. 426-428 - Jae-Sung An, Jong-Hyun Ra, Eunchul Kang, Michiel A. P. Pertijs, Sang-Hyun Han:
28.1 A Capacitive Touch Chipset with 33.9dB Charge-Overflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation and Wireless Power and Data Transfer to an Active Stylus. 430-432 - Hongjae Jang, Hyungcheol Shin, Jaemin Lee, Changwon Yoo, Kanghyup Chun, Ilhyun Yun:
28.2 A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End. 432-434 - Sangwoo Lee
28.3 A 5.2Mpixel 88.4dB-DR 12in CMOS X-Ray Detector with 16b Column-Parallel Continuous-Time ΔΣ ADCs. 434-436 - Doohwan Jung, Sagar Ramesh Kumashi, Jong Seok Park, Sara Tejedor Sanz
28.4 A CMOS Multimodality In-Pixel Electrochemical and Impedance Cellular Sensing Array for Massively Paralleled Synthetic Exoelectrogen Characterization. 436-438 - Ritesh Jain, Philipp Hillger, Janusz Grzyb, Ullrich R. Pfeiffer
29.1 A 0.42THz 9.2dBm 64-Pixel Source-Array SoC with Spatial Modulation Diversity for Computational Terahertz Imaging. 440-442 - Kaizhe Guo, Patrick Reynaert:
29.2 A 0.59THz Beam-Steerable Coherent Radiator Array with 1mW Radiated Power and 24.1dBm EIRP in 40nm CMOS. 442-444 - Aravind Nagulu, Tingjun Chen, Gil Zussman, Harish Krishnaswamy:
29.3 Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting. 444-446 - Mohammad Khorshidian, Negar Reiskarimian
29.4 High-Performance Isolators and Notch Filters Based on N-Path Negative Transresistance. 446-448 - Cheng Wang, Xiang Yi, Mina Kim, Ruonan Han:
29.5 Sub-THz CMOS Molecular Clock with 43ppt Long-Term Stability Using High-Order Rotational Transition Probing and Slot-Array Couplers. 448-450 - Gabriel Guimaraes, Patrick Reynaert:
29.6 A 660-to-676GHz 4×2 Oscillator-Radiator Array with Intrinsic Frequency-Filtering Feedback for Harmonic Power Boost Achieving 7.4dBm EIRP in 40nm CMOS. 450-452 - Kyung-Sik Choi, Dzuhri Radityo Utomo, Keun-Mok Kim, Byeonghun Yun, Sang-Gug Lee, In-Young Lee:
29.7 A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL. 452-454 - Soner Sonmezoglu
34.4 A 4.5mm3 Deep-Tissue Ultrasonic Implantable Luminescence Oxygen Sensor. 454-456 - Mohamed I. Ibrahim
29.8 THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz. 454-456 - Pouyan Bassirian, Divya Duvvuri, Daniel S. Truesdell, Ningxi Liu, Benton H. Calhoun, Steven M. Bowers
30.1 A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band. 460-462 - Jongsoo Lee, Jae-Yeol Han, Chilun Lo, Jongmi Lee, Wan Kim, Seungjin Kim, Byoungjoong Kang, Juyoung Han, Sangdon Jung, Takahiro Nomiyama, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution. 462-464 - Huimin Guo, Tat Fu Chan, Yat Tung Lai, Kam Chuen Wan, Lu Chen, Wai Po Wong:
30.3 A SAW-Less NB-IoT RF Transceiver with Hybrid Polar and On-Chip Switching PA Supporting Power Class 3 Multi-Tone Transmission. 464-466 - Bart J. Thijssen, Eric A. M. Klumperink, Philip Quinlan, Bram Nauta
30.4 A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI. 466-468 - Masahisa Tamura, Hideyuki Takano, Satoru Shinke, Hiroaki Fujita, Hironori Nakahara, Norihito Suzuki, Yutaka Nakada, Yusuke Shinohe, Shinichirou Etou, Tetsuya Fujiwara, Yasushi Katayama:
30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI. 468-470 - Elbert Bechthum, Johan Dijkhuis, Ming Ding, Yuming He, Johan H. C. van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata, Minyoung Song
30.6 A Low-Power BLE Transceiver with Support for Phase-Based Ranging, Featuring 5µs PLL Locking Time and 5.3ms Ranging Time, Enabled by Staircase-Chirp PLL with Sticky-Lock Channel-Switching. 470-472 - Abdullah Mohammed Alghaihab, Xing Chen, Yao Shi, Daniel S. Truesdell, Benton H. Calhoun, David D. Wentzloff:
30.7 A Crystal-Less BLE Transmitter with -86dBm Freq µ ency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet. 472-474 - Minyoung Song
30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills. 474-476 - Jong-Hyeok Yoon, Arijit Raychowdhury:
31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics. 478-480 - Yuqi Su, Hyunjoon Kim
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems. 480-482 - Tianyu Jia, Yuhao Ju, Jie Gu:
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. 482-484 - Sung-Wan Hong:
32.1 A 13.56MHz Current-Mode Wireless Power and Data Receiver with Efficient Power Extracting Controller and Energy-Shift Keying Technique for Loosely Coupled Implantable Devices. 486-488 - Adrien Morel, Anthony Quelen, Carlos Augusto Berlitz
32.2 Self-Tunable Phase-Shifted SECE Piezoelectric Energy-Harvesting IC with a 30nW MPPT Achieving 446% Energy-Bandwidth Improvement and 94% Efficiency. 488-490 - Anthony Quelen, Gaël Pillonnet
32.3 Electromagnetic Mechanical Energy-Harvester IC with No Off-Chip Component and One Switching Period MPPT Achieving up to 95.9% End-to-End Efficiency and 460% Energy-Extraction Gain. 490-492 - Jun-Eun Park, Jeongho Hwang
32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement. 492-494 - Bhushan Talele, Raveesh Magod
32.5 A Scalable and PCB-Friendly Daisy-Chain Approach to Parallelize LDO Regulators with 2.613% Current-Sharing Accuracy Using Dynamic Element Matching for Integrated Current Sensing. 494-496 - Weier Wan
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. 498-500 - Qi Liu, Bin Gao, Peng Yao, Dong Wu, Junren Chen
33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing. 500-502 - Masanori Hashimoto
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. 502-504 - Kyoungtae Lee
34.1 A 64×64 Implantable Real-Time Single-Charged-Particle Radiation Detector for Cancer Therapy. 506-508 - Jeong Hoan Park, Joanne Si Ying Tan, Han Wu
34.2 1225-Channel Localized Temperature-Regulated Neuromorphic Retinal-Prosthesis SoC with 56.3nW/Channel Image Processor. 508-510 - Zhanghao Yu, Joshua C. Chen
34.3 An 8.2mm3 Implantable Neurostimulator with Magnetoelectric Power and Data Transfer. 510-512 - Jiamin Li, Yilong Dong, Jeong Hoan Park, Longyang Lin, Tao Tang, Miaolin Zhang, Han Wu
34.5 Human-Body-Coupled Power-Delivery and Ambient-Energy-Harvesting ICs for a Full-Body-Area Power Sustainability. 514-516 - Tao Tang, Long Yan, Jeong Hoan Park, Han Wu
34.6 EEG Dust: A BCC-Based Wireless Concurrent Recording/Transmitting Concentric Electrode. 516-518
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