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9th LASCAS 2018: Puerto Vallarta, Mexico
- 9th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2018, Puerto Vallarta, Mexico, February 25-28, 2018. IEEE 2018, ISBN 978-1-5386-2311-4
- Pedro A. D. Riveros, Eduardo C. Silva:
High sensitivity GMI gradiometer with an active interference compensation system. 1-4 - Guillermo Antúnez-Calistro, Mariana Siniscalchi
, Fernando Silveira, Conrado Rossi-Aicardi:
Variability-aware design method for a constant inversion level bias current generator. 1-4 - Martin Causa, Franco La Paz, Santiago Radi, Juan Pablo Oliver, Leonardo Steinfeld, Julian Oreggioni
A 64-channel wireless EEG recording system for wearable applications. 1-4 - Sundarapandian Vaidyanathan, Esteban Tlelo-Cuautle
A new four-dimensional chaotic system with hidden attractor and its circuit design. 1-4 - Roberto M. Passos, Gabriel B. B. Ribeiro, Maike M. Muzitano, Lucas B. Nazareth, José Antonio Apolinário
On real-time implementation of the BNLMS algorithm using the SHARC ADSP-21489. 1-4 - A. Martinez-Nieto, Nicolás Medrano, María Teresa Sanz-Pascual
An accurate analysis method for complex IC analog neural network-based systems using high-level software tools. 1-4 - Alexandre de Vasconcelos Cardoso, Nadia Nedjah
Co-design system for template matching using dedicated co-processor and modified elephant herding optimization. 1-4 - Luciano L. Caimi
Runtime creation of continuous secure zones in many-core systems for secure applications. 1-4 - Thiago Bubolz, Ruhan A. Conceição, Mateus Grellert
Fast and energy-efficient HEVC transrating based on frame partitioning inheritance. 1-4 - F. Montalvo-Galicia, María Teresa Sanz-Pascual
High-precision self-compensated fully-integrated CMOS LDO regulator. 1-4 - Yao-Ming Kuo
Educational design kit for synopsys tools with a set of characterized standard cell library. 1-4 - Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez:
Jitter tolerance acceleration using the golden section optimization technique. 1-4 - Filipe Guimarães Russo Ramos, Tales Cleber Pimenta, Luis Henrique de Carvalho Ferreira:
Design of a low-cost and high-performance digital PWM controller for DC-DC converters. 1-4 - Karolinne B. Brito, Robson Nunes de Lima
A 2.45 GHz CMOS active quasi-circulator with a built-in rectifier. 1-4 - Walter Jose Lancioni, Fortunato Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo, Carlos Vazquez:
Continuous time full-feedforward MASH 2-2 architecture for sigma-delta modulators. 1-4 - Francisco Veirano, Pablo Perez-Nicoli, Pablo Castro-Lisboa, Fernando Silveira:
Gate drive losses reduction in switched-capacitor DC-DC converters. 1-4 - Marcus Prochaska
A readout concept for AC-driven xMR sensors in automotive wheel speed applications. 1-4 - Bruno S. Oliveira, Rafael Schild Reusch, Henrique Martins Medina, Fernando Moraes
Evaluating the cost to cipher the NoC communication. 1-4 - Luciana Mendes da Silva, Guilherme Bontorin, Ricardo Reis
Reducing the amount of transistors by gate merging. 1-4 - Sabi Y. M. Bandiri, F. R. R. Marante, Tales Cleber Pimenta, Danilo Henrique Spadoti
Energy consumption improvement based on adaptive FEC code in elastic optical network. 1-4 - Florent Torres
90° Hybrid coupler design technique for wideband and multimode mm-wave operations featuring lateral ground planes virtual expansion in 28nm FD-SOI CMOS technology. 1-4 - Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas Moura Santana, Lester de Abreu Faria:
A novel state assignment method for XBM AFSMs without the essential hazard assumption. 1-4 - Murilo R. Perleberg
ASIC power-estimation accuracy evaluation: A case study using video-coding architectures. 1-4 - M. T. Kousoulis, Constantine A. Coutras, G. E. Antoniou:
Minimum multiplier-delay 4D digital filter. 1-4 - Higor A. Delsoto, Duarte Lopes de Oliveira, Lucas Moura Santana, Lester de Abreu Faria:
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption. 1-4 - Laura Medina-Marin, Ramón Parra-Michel, Aldo G. Orozco-Lugo, M. Mauricio Lara:
Analysis of packet arrival model for 802.11 protocol under hidden terminals and asynchronous MPR detection. 1-4 - Duarte Lopes de Oliveira, Kledermon Garcia, Lucas Moura Santana, Lester de Abreu Faria:
FPGA implementation of high-performance asynchronous pipelines with robust control. 1-4 - Ali Far:
Sub-1 volt class AB amplifier with low noise, ultra low power, high-speed, using winner-take-all. 1-4 - Marcio Monteiro, Ismael Seidel, José Luís Güntzel:
On the calculation reuse in hadamard-based SATD. 1-4 - Mouna Kotti, Mourad Fakhfakh, Esteban Tlelo-Cuautle
Effect of the design space sampling on the design performances. 1-4 - Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt
Reliability evaluation of circuits designed in multi- and single-stage versions. 1-4 - L. Orozco-Galvan, Ramón Parra-Michel, Fernando Peña-Campos, Rodrigo Jaramillo-Ramirez, Eduardo Romero-Aguirre:
A resource efficient symbol synchronizer implementation for the IEEE 802.11 protocol. 1-4 - Luighi A. Viton Zorrilla
Low-power embedded readout and processing system for ISFET sensors as measurement devices. 1-4 - J. M. Sanchez-Venegas, Abisai Ramirez-Perez, Ramón Jaramillo-Ramirez, Ramón Parra-Michel:
An all-digital physical and MAC layer architectures for a reconfigurable Bluetooth transmitter. 1-4 - Shrikant Singh, Debashis Mandal, Bertan Bakkaloglu
Sense resistor-free analog power sensor for boost converter with 14.1% gain error and 9.4% offset error. 1-4 - Chia-Chun Tsai:
Embedded bus switches on 3D data bus for critical access time reduction. 1-4 - Javier Ardila
Stochastic resonance in bang-bang phase detector gain and the impact on CDR locking. 1-4 - C. H. Rodriguez, José Luis Naredo, Omar Longoria-Gandara, Ramón Parra-Michel:
Modeling of microstrip interconnects with cylindrical sub-conductors. 1-4 - Hua Fan, Jingxuan Yang, Franco Maloberti, Quanyuan Feng, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari
High-resolution ADCs design in sensors. 1-4 - Aminadabe dos Santos Pires Soares, Wemerson Delcio Parreira
Energy-based voice activity detection algorithm using Gaussian and Cauchy kernels. 1-4 - Marco Antonio Gurrola-Navarro
Frequency-domain interpolation for simultaneous periodic nonuniform samples. 1-4 - Leonardo Bandeira Soares, Morgana M. A. da Rosa, Cláudio Machado Diniz, Eduardo A. C. da Costa
Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering. 1-4 - Lucas de Paris, Ricardo Reis
An automated methodology to fix electromigration violations on a customized design flow. 1-4 - Elias de Almeida Ramos, Guilherme Bontorin, Ricardo Reis
A nonlinear placement for FPGAs: The chaotic place. 1-4 - Roman Fragasse
Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs. 1-5 - Olivier Bonnaud, Laurent Fesquet, Luc Hébrard:
Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. 1-4 - Angel Abusleme
A baseline restorer for charge-sensitive amplifiers in a 500-nm CMOS process. 1-4 - Braulio Cancino, Angel Abusleme
A novel current-based CCD clock driver. 1-4 - Douglas Lohmann, Fabrizio Maziero, Elço João dos Santos Jr
Extending universal verification methodology with fault injection capabilities. 1-4 - Jorge Augusto Costa
CMOS analog front-end IC for EEG applications with high powerline interference rejection. 1-4 - Benjamín T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis
An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. 1-4 - Carlos Andres Lara-Nino
Small lightweight hash functions in FPGA. 1-4 - Cecilia Gimeno, Denis Flandre, David Bol:
Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI. 1-4 - Guillermo Royo, Carlos Sánchez-Azqueta
Highly-linear transimpedance amplifier for remote antenna units. 1-4 - Yao-Ming Kuo
Analog front-end design of contactless RFID smart card ISO/IEC14443A standard - Compliant. 1-4 - Jose L. Silva-Perales, Daniel Garcia-Garcia, Carlos J. Franco-Tinoco:
Impedance vs coupling noise analysis and tradeoff on power delivery filters based on package layout interconnections. 1-4 - Gabriel Lobao Fre, Felipe Beltran-Mejia, Tales Cleber Pimenta, Danilo Henrique Spadoti
Low loss air channel modulator for ultra high frequency operation. 1-3 - Ariel Oroz De Gaetano, Martin Di Federico, Ariel Arelovich:
ALPR character segmentation algorithm. 1-4 - Dalton M. Colombo
An approach a new 1 V supply resistorless voltage reference using Schottky diode. 1-4 - F. Tubiello, Leticia Bolzani Poehls, Thais Webber
A path energy control technique for energy efficiency on wireless sensor networks. 1-4 - Lyda V. Herrera, Gordana Jovanovic-Dolecek
Mathieu functions for DFT filter bank spectrum sensing. 1-4 - Adrián Pérez-Resa
Chaos-based stream cipher for gigabit ethernet. 1-4 - Miguel Garcia-Bosque
A new randomness-enhancement method for chaos-based cryptosystem. 1-4 - Jorge Pérez-Bailón
A 1V-1.75μW Gm-C low pass filter for bio-sensing applications. 1-4 - Ali Far:
Class AB amplifier with noise reduction, speed boost, gain enhancement, and ultra low power. 1-4 - Luis A. Rodriguez-Meneses, Celso Gutiérrez-Martínez, Jacobo Meza-Perez, J. Alfredo Torres-Fortiz, Roberto S. Murphy-Arteaga:
Design and construction of dual-mode micro-strip resonator filters for the 950-1, 450 MHz band: Application as IF filters in microwave transceivers. 1-4 - Oscar Danilo Montoya, Alejandro Garces Ruiz
Apparent power control in single-phase grids using SCES devices: An IDA-PBC approach. 1-4 - E. I. Rodriguez, Juan Gerardo Ávalos Ochoa
Error coded affine projection-like algorithm with evolving order and variable resolution for acoustic echo cancellation. 1-4 - G. Diaz-Arango, Hector Eduardo De Cos-Cholula, Luis Hernández-Martínez, F. Castro-Gonzalez, R. Ruiz-Gomez, Hector Vazquez-Leal:
Off-line route planner based on resistive grid method for vehicle guidance in real-time applications. 1-4 - Vinicius Martins, Jerson Paulo Guex, Luciana Shiroma Montali, Jiang Chau Wang:
The functional verification of a satellite transponder. 1-4 - Gordana Jovanovic-Dolecek
Novel two-stage comb filter for multiple-of-three decimation factors. 1-4 - Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy
Optimization-based reconfigurable approach for low-power 3D chip-multiprocessors. 1-4 - Jose Eduardo Chiarelli Bueno Filho
On TLM traffic accuracy: A multifractal perspective. 1-4 - Carlos Alberto Sanabria Diaz, Mónico Linares Aranda:
An analysis of on-silicon-via stacks in RF-CMOS processes. 1-4 - Jonathan Martínez Moreno, Agustín Santiago Medina-Vázquez, Carlos Alberto Bonilla Barragán, José M. Arce-Zavala, José Martín Villegas González:
Experimental analysis of microstrip antennas using techniques to improve the bandwidth. 1-4 - Alejandro Garcia-Santiago, Josefina Castañeda-Camacho, José-Fermi Guerrero-Castellanos, Gerardo Mino Aguilar:
Evaluation of AODV and DSDV routing protocols for a FANET: Further results towards robotic vehicle networks. 1-4 - Arturo Sarmiento-Reyes, Yojanes Rodriguez-Velasquez:
Maze-solving with a memristive grid of charge-controlled memristors. 1-4 - Angelos Giakoumis, Christos K. Volos, Jesús Manuel Muñoz-Pacheco
Text encryption device based on a chaotic random bit generator. 1-5 - Lucas C. Severo
A 10.9-μW/pole 0.4-V active-RC complex BPF for Bluetooth low energy RF receivers. 1-4 - Fernando Martins Cardoso, Márcio Cherem Schneider, Edson Pinto Santana:
CMOS analog multiplier with high rejection of power supply ripple. 1-4 - Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers, Gerd Ascheid:
VLSI implementation of channel estimation for millimeter wave beamforming training. 1-4 - Juan Luis Castagnola
Design and optimisation of a cascode low noise amplifier (LNA) using MOST scattering parameters and gm/ID ratio. 1-4 - Satomi Ogawa, Takahide Sato:
A high-accuracy capacitance-to-time converter for capacitive sensors. 1-4 - Sidartha A. L. Carvalho, Lucas M. F. Harada, Rafael N. Lima, Carolina M. A. Barbosa, Daniel C. Cunha, Abel G. Silva-Filho:
Identifying power consumption signatures in LTE conformance tests using machine learning. 1-4 - Marina Sparvoli
Resistive switching phenomenon in graphene oxide doped with copper devices. 1-4 - Shrief Rizkalla, Ralph Prestros, Christoph F. Mecklenbräuker:
A simplified reference proximity integrated circuit card for HF RFID. 1-4 - Ali Shiri Sichani, Wilfrido A. Moreno:
Mathematical model for glitch power consumption to study its implication on power analysis attacks. 1-4 - Felipe Rocha da Rosa, Ricardo Reis, Luciano Ost
gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations. 1-4
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