default search action
13th SBCCI 2000: Manaus, Brazil
- Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000. IEEE Computer Society 2000, ISBN 0-7695-0843-X
- Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. 3-8 - Walid Maroufi, Mounir Benabdenbi, Meryem Marzouki:
Solving the I/O Bandwidth Problem in System on a Chip Testing. 9-14 - André Inácio Reis, A. Prado, Marcelo Lubaszewski:
Testability Properties of Vertex Precedent BDDs. 15-20 - José Luís Güntzel, Ana Cristina Medina Pinto, Eduardo D'Avila, Ricardo Reis:
ATG-Based Timing Analysis of Circuits Containing Complex Gates. 21-28 - Roberto d'Amore:
A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification Unit. 29-34 - Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija:
Partitioned Branch Condition Resolution Logic. 35-40 - Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha:
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. 41-46 - Sergio C. Salomão, João M. S. Alcântara, Vladimir Castro Alves, Felipe M. G. França:
Improved IDEA. 47-54 - Kunio Okuda, Siang W. Song:
Revisiting Hamiltonian Decomposition of the Hypercube. 55-60 - Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj:
An Input-Output Encoding Approach for Serial Decomposition. 61-68 - Malgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske:
Disjunctive Decomposition of Switching Functions Using Symmetry Information. 69-74 - Paulo Maciel, Fred Cruz Filho, Edna Barros, Wolfgang Rosenstiel:
Methods Based on Petri Net for Resource Sharing Estimation. 75-82 - Achim Graupner, René Schüffny:
Robust Implementation and Statistical Modeling of a VI-Converter. 83-88 - Carlos Galup-Montoro, Márcio C. Schneider:
Resizing Rules for the Reuse of MOS Analog Designs. 89-93 - Fernando Silveira, Denis Flandre:
Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers. 94-98 - André Luiz Aita, Sergio Bampi, Jung Hyun Choi:
A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor Array. 99-106 - Carlos A. Alba Pinto, Koen van Eijk, Bart Mesman, Jochen A. G. Jess:
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms. 107-112 - Qin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess:
Register Binding for Predicated Execution in DSP Applications. 113-118 - J. Perez R. Cost, José Vieira do Vale Neto:
A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC). 119-124 - Leandro Soares Indrusiak, Ricardo Augusto da Luz Reis:
From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project. 125-132 - João Leonardo Fragoso, Fernando Moraes, Ricardo Reis:
WTROPIC: A WWW-Based Macro-Cell Generator. 133-138 - Alexander Tiountchik, Elena Trichina:
Modular Exponentiation on Fine-Grained FPGA. 139-143 - Marcelo O. Johann, Ricardo Reis:
Net by Net Routing with a New Path Search Algorithm. 144-149 - Peter Glösekötter, Christian Pacha, Karl F. Goser, Gilson I. Wirth, Werner Prost, Uwe Auer, M. Agethen, P. Velling, Franz-Josef Tegude:
Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor. 150-158 - Ivan Jeukens, Marius Strum:
On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs. 159-164 - Victor M. Goulart Ferreira, Hiroto Yasuura:
Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs. 165-170 - Reinaldo Silveira, Wilhelmus A. M. Van Noije:
Modeling an E1/TU12 Mapper for SDH Systems. 171-176 - Ricardo Pezzuol Jacobi, F. Trindade, José Porfírio A. de Carvalho, R. Cantanhede:
JPEG Decoding in an Electronic Voting Machine. 177-184 - José Antônio Gomes de Lima, Elmar U. K. Melchier, Hamilton Soares da Silva:
An FPGA Implementation of the ATM Layer. 185-190 - Gustavo Adolfo Cerezo Vasquez, Wilhelmus A. M. Van Noije, Silvio E. Barbin:
Prototyping a Pager-Like Device Using FPGAs: Design of an Object Finder. 191-196 - B. Dulny, Jürgen Fent, Werner Haberer, Christian Kiesling, A. Osthoff:
Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate Arrays. 197-201 - René Zapata, Pascal Lépinay, L. Torres, Jacques Droulez, Vincent Creuze:
Prototyping of a Biologically-Plausible Vision System for Robotic Applications. 202-210 - Nikola Nedovic, Vojin G. Oklobdzija:
Hybrid latch Flip-Flop with Improved Power Efficiency. 211-215 - Luciano Agostini, Georg Stemmer, A. Prado, Roberto Pacheco, T. Campos, Sergio Bampi, Ricardo Reis:
SisECO: Design of an Echo-Canceling IC for Base Band Modems. 216-221 - Eduardo A. C. da Costa, Fernando Paixão Cortes, Rodrigo Ferrugem Cardoso, Luigi Carro, Sergio Bampi:
Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels. 222-227 - Joao Navarro Soares, Wilhelmus A. M. Van Noije:
The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput. 228-236 - Lorena Anghel, Dan Alexandrescu, Michael Nicolaidis:
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. 237-242 - Régis Leveugle, K. Hadjiat:
Optimized Generation of VHDL Mutants for Injection of Transition Errors. 243-248 - Fabian Vargas, Alexandre M. Amory:
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis. 249-254 - Fernanda Gusmão de Lima, Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Ricardo Reis, Raoul Velazco, Sana Rezgui:
Designing a Radiation Hardened 8051-Like Micro-Controller. 255-262 - C. L. Pereira, Diogenes C. da Silva Júnior, R. G. Duarte, Antônio Otávio Fernandes, L. H. Canaan, Claudionor José Nunes Coelho Jr., L. L. Ambrosio:
JADE: An Embedded Systems Specification, Code Generation and Optimization Tool. 263-268 - Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin:
An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. 269-274 - Daniel W. Engels, Srinivas Devadas:
A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design. 275-280 - Rolf Fredi Molz, Paulo Martins Engel, Fernando Gehm Moraes, Lionel Torres, Michel Robert:
Design of a Classification System for Rectangular Shapes Using a Co-Design Environment. 281-288 - José Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski, Antonio Carneiro de Mesquita Filho:
Fault Models and Compact Test Vectors for MOS OpAmp circuits. 289-294 - Yann Deval, Jean-Baptiste Bégueret, Jean Tomas, Pascal Fouillat:
Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of Experiments. 295-300 - Jochen Mades, Thomas Schneider, Manfred Glesner, André Windisch, Wolfgang Ecker:
A JAVA-Based Mixed-Signal Design Environment. 301-306 - Testing Mixed-Signal Cores. 307-314
- Lou Scheffer:
What is the Appropriate Model for Crosstalk Control? 315-320 - José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda:
Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. 321-326 - F. K. Ferreira, Fernando Moraes, Ricardo Reis:
LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design. 327-332 - Brett Warneke, Kristofer S. J. Pister:
An Integrated Circuit for the in Situ Characterization of CMOS Best-Process Micromachining. 333-340 - Jürgen Becker, Thilo Pionteck, Manfred Glesner:
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. 341-346 - Iouliia Skliarova, António de Brito Ferrari:
Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable Computations. 347-352 - Valery Sklyarov:
Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs. 353-358 - Holger Singpiel, Harald Simmler, Andreas Kugel, Reinhard Männer, Antônio C. C. Vieira, Federico Gálvez-Durand, João M. S. Alcântara, Vladimir Castro Alves:
Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable. 359-364 - A. Forestier, Mircea R. Stan:
Limits to Voltage Scaling from the Low Power Perspective. 365-370 - Robert Siegmund, Claudia Kretzschmar, Dietmar Müller:
Adaptive Partial Businvert Encoding for Power Efficient Data Transfer over Wide System Buses. 371-376 - Jessica H. Tseng, Krste Asanovic:
Energy-Efficient Register Access. 377-384 - Klaus D. Müller-Glaser, Eric Sax, Wilhelm Stork, A. Wagner, J. Drescher, Markus Kühl:
Design and Simulation of Heterogeneous Embedded Systems. 385-390 - Sérgio Akira Ito, Júlio C. B. de Mattos, Luigi Carro, Simão S. Toscani:
A Comparison of OO and Reactive Based Specifications on the Design of Embedded Systems. 391-396 - Sérgio Akira Ito, Luigi Carro:
A Comparison of Microcontrollers Targeted to FPGA-Based Embedded Applications. 397-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-04 20:31 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: