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42nd VTS 2024: Tempe, AZ, USA
- 42nd IEEE VLSI Test Symposium, VTS 2024, Tempe, AZ, USA, April 22-24, 2024. IEEE 2024, ISBN 979-8-3503-6378-4
- Stephen Traynor, Saidapet Ramesh, Maryfe Hernandez, Lawrence Herr, Scott Chen:
Customizing ATPG User-Defined Stresses and Tests To Target Cell-Neighborhood-Bridging Defects. 1-5 - Raphael Robertazzi, David J. Frank, Kevin Tien, John Timmerwilke, Peilin Song, Daniel J. Friedman:
Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. 1-7 - Chris Nigh, Ronald D. Blanton:
Logic-AAA: Debug of Logic Failures with an on-ATE Expert System. 1-6 - Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu:
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. 1-4 - Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim:
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. 1-11 - Yingyi Luo
, Talha M. Khan
AlN Sputtering Parameter Estimation Using A Multichannel Parallel DCT Neural Network. 1-5 - Arani Sinha, Stefano Di Carlo:
Innovative Practices Track: Session 4 AI Applications in Test. 1 - Saeed Zeinolabedinzadeh:
Millimeter-wave and THz Measurement Practices. 1-4 - Soyed Tuhin Ahmed
NN-ECC: Embedding Error Correction Codes in Neural Network Weight Memories using Multi-task Learning. 1-7 - Mingye Li, Yunkun Lin, Sandeep Gupta:
Built in self test (BIST) for RSFQ circuits. 1-7 - Emre Ulusoy, Bahadir Ozkan, Furkan Barin, Fatih Maden, Ercem Yesil, Dursun Baran, Adem Eren, Tufan Coskun Karalar, Ahmet Tekin, Ertan Zencir:
High Precision Adaptive Calibration Feedback in RF Front-end for Digital Pre-distortion Application. 1-5 - Vahid Rezazadehshabilouyoliya, Muhammed Mustafa Kizmaz, Ahmet Tekin:
Power-up Self Auto Calibration of High Speed SAR Converter in a 22nm FD-SOI CMOS Process. 1-5 - Yiqiang Zhao, Gonsen Qu, Qizhi Zhang, Yao Li, Zhengyang Li, Jiaji He:
Static Gate-Level Information Flow for Hardware Information Security with Bounded Model Checking. 1-7 - Mingyuan Xiang, Xuhan Xie, Pedro Savarese, Xin Yuan, Michael Maire, Yanjing Li:
Drop-Connect as a Fault-Tolerance Approach for RRAM-based Deep Neural Network Accelerators. 1-7 - Rahul Kande, Vasudev Gohil
LLMs for Hardware Security: Boon or Bane? 1-4 - Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management. 1-5 - Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev:
Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. 1-7 - Stephen Sunter, Vladimir Zivkovic, Bartlomiej Praselski:
A Method for Simulating Mixed-Signal ATE Tests. 1-7 - Ian Hill
Enhanced Wear-Out Sensor Design in a 12nm Process for Separable Stress Regime Monitoring. 1-7 - Arani Sinha:
Innovative Practices Track: Session 3 Test and Functional Safety Standards. 1 - Valentin Gherman, Cyrille Laffond:
Sequential Decoders for Binary Linear Block ECCs. 1-5 - Febin Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha:
Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators. 1-4 - D. Wilson, Nad E. Gilbert, Matt Spear, J. Short, Christopher H. Bennett, William Wahby, J. Kim
A Discovery Platform to Characterize Emerging Nonvolatile Memories for Computing. 1-5 - Mohamed Mejri, Chandramouli N. Amarnath, Abhijit Chatterjee:
Error Resilient Hyperdimensional Computing Using Hypervector Encoding and Cross-Clustering. 1-7 - Abdullah Eroglu, M. N. Mahmoud:
Artificial Intelligence Based High Power Calibration Method for RF Pulse Amplifiers. 1-5 - Juan-David Guerrero-Balaguera
Evaluating the Reliability of Supervised Compression for Split Computing. 1-6 - Robert Limas Sierra, Juan-David Guerrero-Balaguera
Analyzing the Impact of Scheduling Policies on the Reliability of GPUs Running CNN Operations. 1-7 - Haruo Kobayashi, Naoki Tsukahara, Keno Sato, Takashi Oshima
Innovative Practices Session at VLSI Test Symposium 2024: Analog Testing Technologies for Digital Exploding Society. 1 - Kai Su, Mark Giraud, Anne Borcherding
Fuzz Wars: The Voltage Awakens - Voltage-Guided Blackbox Fuzzing on FPGAs. 1-7 - Irith Pomeranz:
Test Compaction Using (k, 1)-Cycle Tests. 1-7 - Chandarasekaran Ramamurthy, Harrish Anbazhagan, B. Rajeswara:
Test Methods for TID Effects on Capacitors. 1-4 - Nourhan Elhamawy, Jens Anders, Ilia Polian, Matthias Sauer:
Scenario-based Test Content Optimization: Scan Test vs. System-Level Test. 1-7 - Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. 1-7 - Ishaan Bassi, Sule Ozev:
Calibration and Source Localization Using an Array of Resistive Metal Oxide Gas Sensors. 1-7 - Xunyu Li, Weiquan Hao, Zijin Pan, Yunru Miao, Zijian Yue, Albert Z. Wang:
Practical Considerations on ESD Testing. 1-3 - Fei Su, Jyotika Athavale, Zohaib Khan, Marc Witteman:
Innovation Practices Track: Advances on Silicon Lifecycle Reliability, Safety and Security. 1 - Mingjie Liu, Minwoo Kang, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren:
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification. 1-4 - Sina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM. 1-7 - N. Afroz, A. Sayem, Georgios Volanis, Dzmitry Maliuk, Haralampos-G. Stratigopoulos, Yiorgos Makris:
On the Sensitivity of Analog Artificial Neural Network Models to Process Variation. 1-7 - Ryan F. Forelli, Rui Shi, Seda Ogrenci
A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators. 1-5 - Subashini Gopalsamy
A Storage Based LBIST Scheme for Logic Diagnosis. 1-7 - Mahta Mayahinia, Haneen G. Hezayyin, Mehdi B. Tahoori:
Reliability analysis and mitigation for analog computation-in-memory: from technology to application. 1-7 - Sanjay Das, Shamik Kundu, Anand Menon, Yihui Ren, Shubha R. Kharel
Analyzing and Mitigating Circuit Aging Effects in Deep Learning Accelerators. 1-7 - Gaines Odom
A Novel Self-referencing Approach Using Memory Power-up States for Detecting COTS SRAMs. 1-7 - Apurva Jain, Thomas Broadfoot, Carl Sechen, Yiorgos Makris:
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. 1-7 - Ferhat Can Ataman, Mohammed Aladsani, Y. B. Chethan Kumar, Georgios Trichopoulos, Sule Ozev:
Multi-Parameter Optimization of mm-Wave Antenna Layout Using Hybrid Modeling and Incremental Model Learning. 1-5 - Arani Sinha, Adit D. Singh:
Innovative Practices Track: Session 2 Silent Data Corruption. 1 - Gulroz Singh, Ankit Hegde, Vaibhav Kumar:
Unified Functional Safety Framework for advance multi-domain SoCs combining ISO 26262 & IEC61508. 1-3 - Shao-Chun Hung, Partho Bhoumik, Krishnendu Chakrabarty:
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration. 1-7 - Carl S. Moore:
Innovative Practices Track: Session 7 Yield Optimization, Reducing Costs, and Improving Quality. 1 - Ralf E.-H. Yee, Nicholas Y.-J. Su, Lowry P.-T. Wang, Charles H.-P. Wen
Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics. 1-7 - Tommaso Baldi
Reliable edge machine learning hardware for scientific applications. 1-5 - Duane Brown, Ira Leventhal, Sri Ganta, Keith Schaub:
Innovative Practices Track: Session 6 - Using AI to Address the Silicon Growth Curve. 1 - Abhishek Kumar Mishra, Mohammad Ershad Shaik, Anush Niranjan Lingamoorthy, Suman Kumar, Anup Das, Nagarajan Kandasamy, Nur A. Touba:
WaferCap: Open Classification of Wafer Map Patterns using Deep Capsule Network. 1-7 - Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera
Special Session: Reliability Assessment Recipes for DNN Accelerators. 1-11 - Sumukh Prashant Bhanushali, Tushar Gupta
Machine Learning Based Static and Dynamic Error Calibration in Data Converters. 1-4 - Jaehyun Park, Alish Kanani
Thermal Modeling and Management Challenges in Heterogenous Integration: 2.5D Chiplet Platforms and Beyond. 1-4
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