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VLSI-DAT 2013: Hsinchu, Taiwan
- 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. IEEE 2013, ISBN 978-1-4673-4435-7
- Chia-Yu Yao, Yung-Hsiang Ho:
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism. 1-4 - Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan:
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V. 1-4 - Jia-Hua Hong, Ming-Chun Liang, Jing-Yi Wong, Shuenn-Yuh Lee:
A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications. 1-4 - Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura:
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. 1-4 - Hang Lv, Bo Zhou, Dang Liu, Woogeun Rhee
, Yongming Li, Zhihua Wang:
A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems. 1-4 - Ching-Che Chung
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. 1-4 - Guo-An Jian, Jui-Sheng Lee, Kheng-Joo Tan, Peng-Sheng Chen, Jiun-In Guo:
A real-time parallel scalable video encoder for multimedia streaming systems. 1-4 - Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay:
A fast and accurate instruction-oriented processor simulation approach. 1-5 - Ta-Kan Yen, Hsien-Kai Kuo, Bo-Cheng Charles Lai:
A distributed thread scheduler for dynamic multithreading on throughput processors. 1-4 - Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay:
A Cycle Count Accurate TLM bus modeling approach. 1-4 - Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Worst-case IR-drop monitoring with 1GHz sampling rate. 1-4 - Rodd Novak:
UltraCMOS® technology for high-performance switch paths and tunable components. 1 - Hitoshi Mizunuma, Yi-Chang Lu
Thermal coupling aware task migration using neighboring core search for many-core systems. 1-4 - Wen Chen, Li-C. Wang
Novel test analysis to improve structural coverage - A commercial experiment. 1-4 - Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai:
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. 1-4 - Federico A. Altolaguirre, Ming-Dou Ker:
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. 1-4 - Wenhui Zhao, Grantham K. H. Pang, Ngai Wong:
Automatic adaptive multi-point moment matching for descriptor system model order reduction. 1-4 - Bo-Ting Yeh, Chun-Hung Yang, Kai-Cheung Juang, Chien-Hung Tsai:
Sensorless dead-time exploration for digitally controlled switching converters. 1-4 - Jiann-Ching Guey:
To 4G mobile communication and beyond. 1-2 - Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. 1-4 - Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin
A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer. 1-4 - Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang:
Time-domain analog-to-digital converters with domino delay lines. 1-4 - Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen:
Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. 1-4 - Sying-Jyan Wang
Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. 1-4 - Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, Chung-Wei Yeh:
Electromigration- and obstacle-avoiding routing tree construction. 1-4 - Diego Olego:
Innovations in healthcare and semiconductor progress. 1 - Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng:
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. 1-4 - Ted Chang:
In and out of the cloud. 1 - Shyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng:
Efficient test and repair architectures for 3D TSV-based random access memories. 1-4 - Thomas Lee:
Terahertz electronics: Opportunities, challenges and technologies. 1 - Ting-Zi Chen, Soon-Jyh Chang, Guan-Ying Huang:
A successive approximation ADC with resistor-capacitor hybrid structure. 1-4 - Bill Penner:
Multi-processor debug in SoC and processor designs. 1 - Sachin S. Sapatnekar
What happens when circuits grow old: Aging issues in CMOS design. 1-2 - Lei Wang, Chun-Huat Heng
A sub-GHz mostly digital impulse radio UWB transceiver for wireless body sensor networks. 1-4 - Vida Ilderem:
M2M: Challenges and opportunities. 1 - Chun-Yi Yeh, Hung-Chih Chiu, Hsi-Pin Ma:
An information hub for implantable wireless brain machine interface. 1-4 - Caleb Y.-S. Cho, J. C. Wang, Lion Huang, Milo Weng, Yu-Fan Lin, Chia-Fu Lee, C. W. Lien, H. C. Feng, Tassa Yang, S. P. Liao, J. J. Wu, Yu-Der Chih, Sreedhar Natarajan:
A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash. 1-4 - Yin-Chi Peng, Chien-Chih Chen, Chia-Jung Chang, Tien-Fu Chen, Pen-Chung Yew
Cross-layer dynamic prefetching allocation strategies for high-performance multicores. 1-4 - Min Tan, Wing-Hung Ki
Current-mirror miller compensation: An improved frequency compensation technique for two-stage amplifiers. 1-4 - Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang
Power and area reduction in multi-stage addition using operand segmentation. 1-4 - Barry P. Linder, Eduard Cartier, S. Krishnan, Ernest Y. Wu:
Improving and optimizing reliability in future technologies with high-κ dielectrics. 1-4 - Chin-Yu Lin, Tai-Cheng Lee:
Jitter error cancellation technique in digital domain for ADC. 1-4 - Hongyi Wang, Xi Hu, Quanfeng Liu, Gangdong Zhao, Dongzhe Luo:
A novel on-chip current-sensing structure for current-mode DC-DC converter. 1-4 - Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A process-scalable RF transmitter using 90nm and 65nm Si CMOS. 1-4 - Laurent Le-Pailleur:
FDSOI: A differentiator for application processors in consumer and mobile markets. 64 - Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. 1-4 - Kuan-Hung Chen:
Reducing computation redundancy for high-efficiency view synthesis. 1-4 - Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang
Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems. 1-4 - Chih-Ting Yeh, Ming-Dou Ker:
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. 1-4 - Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling. 1-4 - Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang:
On the futility of thermal through-silicon-vias. 1-6 - Shingo Yamanouchi, Kazuaki Kunihiro, Shinichi Hori, Masao Ikekawa, Naoki Nishi:
RF and signal processing technologies for 4G mobile networks. 1-2 - Sanjeev Jain, Sheng-Lyang Jang, Miin-Horng Juang:
A 4.0/7.5-GHz dual-band LC VCO in 0.18-μm SiGe BiCMOS technology. 1-4 - R. Yuan, Shanq-Jang Ruan, Jürgen Götze:
A practical NoC design for parallel DES computation. 1-4 - Erik Jan Marinissen
Creating options for 3D-SIC testing. 1-7 - Yi-Keng Hsieh, Hsieh-Hung Hsieh, Liang-Hung Lu:
A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS. 1-4 - Cosette Y. H. Lin, Ryan H.-M. Huang, Charles H.-P. Wen, Austin C.-C. Chang:
Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs. 1-4 - Jui-Chieh Liao, Wei-Yeh Shih, Kuan-Ju Huang, Wai-Chi Fang:
An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejection. 1-4 - Tanya Nigam:
CMOS reliability: From discrete device degradation to circuit aging. 1 - Makiko Ito, Mitsuru Tomono, Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Yoshio Hirose:
A novel processor design flow using processor description language applied to a vector coprocessor. 1-4 - Ting-Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips. 1-4 - Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee:
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. 1-4 - Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang:
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. 1-4 - Mu-Hsuan Chuang, Yi-Hao Lo, Bo-Yi Wu, Yuan-Hao Huang:
MIMO fingerprinting-based particle filter for mobile positioning systems. 1-4 - Kun-Chih Chen
Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems. 1-4 - Kuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang:
An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip. 1-4 - Gennadi Bersuker:
Microscopic degradation models for advanced technology. 1 - Eric Chang, Frankie Liu, Philip Amberg, Jon K. Lexau, Ron Ho:
Efficient techniques for canceling transceiver noise. 1-4 - Shin-ya Abe, Youhua Shi
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. 1-4 - John Goodacre:
ARM next generation 64bit processors for power efficient compute. 1 - Chen-Yu Wang, Jhih-Sian Guo, Chi-Yuan Huang, Chien-Hung Tsai:
A high effieciency DC/DC boost regulator with adaptive off/on-time control. 1-4 - Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino:
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. 1-4 - James P. Young, Nick Cheng:
Multimode multiband power amplifier optimization for mobile applications. 1-3 - Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo
Improve speed path identification with suspect path expressions. 1-4 - Zong-Han Yang, Tsung-Yi Ho
Timing-aware clock gating of pulsed-latch circuits for low power design. 1-4 - Hsien-Hsin Sean Lee:
The quest for a new dimension of system integration. 16 - Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. 1-4 - Chun-Hung Lai, Yun-Chung Yang, Ing-Jer Huang:
A versatile data cache for trace buffer support. 1-4 - Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen:
A configurable bus-tracer for error reproduction in post-silicon validation. 1-4 - Tsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu:
A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications. 1-4 - Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu:
A background calibration technique for fully dynamic flash ADCs. 1-4 - Yu-Jie Fu, Guan-Lin Wu, Shao-Yi Chien
Real-time salient object detection engine for high definition videos. 1-4 - Chung-Ming Huang, Wei-Da Guo, Chia-Re Shen, Chih-Chung Tsai:
Silicon-package-board co-design for the eye diagram prediction of a 3Gbps HDMI transmitter. 1-3 - Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai:
Enabling inter-die co-optimization in 3-D IC with TSVs. 1-4 - Ding-Yun Chen, Chi-Cheng Ju, Chen-Tsai Ho, Chung-Hung Tsai:
MVSE: A Multi-core Video decoder System level analytics Engine. 1-4 - Do-Gyoon Song, Jaeha Kim:
A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines. 1-4 - Jeong-Tyng Li:
Design challenges for analog & mixed signal designs. 1-2 - Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A view scalable multi-view video decoder system. 1-4 - Ching-Che Chung
A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. 1-4 - Chin Yin, Chih-Cheng Hsieh:
A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring. 1-4 - Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu:
A layout-aware automatic sizing approach for retargeting analog integrated circuits. 1-4 - Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu:
Case study of yield learning through in-house flow of volume diagnosis. 1-4 - Jheng-Hao Ye, Tsung-Wei Hung, Ming-Der Shieh:
Energy-efficient architecture for word-based Montgomery modular multiplication algorithm. 1-4
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last updated on 2025-01-27 20:31 CET by the dblp team
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