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IEEE Transactions on Very Large Scale Integration Systems, Volume 33
Volume 33, Number 1, January 2025
- Hyoseok Song
, Kwangmin Kim
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. 1-9 - Jie Ding
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. 10-20 - Haitao Du
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. 21-34 - Haiyue Yan
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. 35-46 - Yu Liu
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. 47-51 - Tianzhu Xiong
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. 52-65 - Zhen Gao
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. 66-74 - Seung-Hwan Bae, Hyuk-Jae Lee
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution. 75-87 - Jie Li, Chuanlun Zhang, Wenxuan Yang, Heng Li, Xiaoyan Wang, Chuanjun Zhao, Shuangli Du, Yiguang Liu:
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation. 88-101 - Zhichao Chen
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. 102-113 - Anawin Opasatian
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier. 114-127 - Ken Li
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. 128-139 - Tianning Gao
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. 140-153 - Jinghai Wang
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. 154-167 - Jhe-En Lin
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. 168-178 - Dhandeep Challagundla
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory. 179-192 - Dongkwun Kim
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor. 193-206 - Chuanning Wang
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. 207-220 - Zhe Huang
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V. 221-233 - Zhaolin Yang
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. 234-247 - Shuming Guo, Yinyin Lin
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. 248-260 - Xingye Liu
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation. 261-274 - Alexandre Almeida da Silva
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC. 275-287 - Lakshmi Bhanuprakash Reddy Konduru
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. 288-292 - Zhihao Zhou
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes. 293-297 - Yiwei Chang
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks. 298-302
Volume 33, Number 2, February 2025
- Zhan Qu
Multiobjective Optimization of Class-F Oscillators. 303-314 - Shiro Dosho
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier. 315-325 - Chiara Venezia
46-nA High-PSR CMOS Buffered Voltage Reference With 1.2-5 V and -40 ◦C to 125 ◦C Operating Range. 326-336 - Ebenezer C. Usih
Toggle SOT-MRAM Architecture With Self-Terminating Write Operation. 337-345 - Sudipta Das
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. 346-357 - Gauthaman Murali
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators. 358-370 - Lixun Wang
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices. 371-383 - Tiancheng Cao
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications. 384-394 - Shushi Chen
An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC. 395-407 - Yazheng Tu
SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC. 408-420 - Ruichang Jiang
Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA. 421-434 - Chao Ji
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation. 435-448 - Ruijun Ma
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. 449-461 - Seung Ho Shin
Effective Parallel Redundancy Analysis Using GPU for Memory Repair. 462-474 - Shuo Cai
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. 475-487 - Youngki Moon
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM. 488-498 - Huarun Chen
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform. 499-511 - Zhiquan Wan
Architectural Exploration for Waferscale Switching System. 512-524 - Yuanbo Wang, Liang Chang
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique. 525-536 - Akhil Reddy Pakala
MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator. 537-545 - Jia-Li Duan
SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA. 546-557 - Pedro Tauã Lopes Pereira
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. 558-562 - Dingyang Zou
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators. 563-567 - Wanbin Zha
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors. 568-572 - Yuxin Ji
A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI. 573-577 - Chenjia Xie
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations. 578-582 - Quanzhen Liang
Analysis and Design of Wideband GaAs Digital Step Attenuators. 583-587 - Zihang Wang, Yushu Yang, Jianfei Wang
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering. 588-592 - Jiliang Liu
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. 593-597 - Jahyun Koo
A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. 598-602
Volume 33, Number 3, March 2025
- Mircea R. Stan:
Editorial: Renewed Excellence for 2025-2026. 603-626 - Changle Zhi, Gang Dong, Deguang Yang, Daihang Liu, Yinghao Feng, Yang Wang, Zhangming Zhu:
Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits. 627-637 - Felix Burkhardt, Florian Protze, Frank Ellinger:
A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line Networks. 638-650 - Yuhong Lu, Ting-An Yen, Rakshit Dambe Nayak, Shashank Alevoor, Bhushan Talele, Spoorti Patil, Keith Kunz, Bertan Bakkaloglu:
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs. 651-661 - Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim:
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. 662-672 - Yechen Tian, Yutong Zhang, Junjie Gu, Hao Xu, Weitian Liu, Rui Yin, Zongming Duan, Hao Gao, Na Yan:
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver. 673-684 - Weihao Wang, Kong-Pang Pun:
An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop. 685-696 - Srishti Agrawal, Rakesh Kumar Palani, Sweta Tripathi:
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars. 697-706 - Zhaoteng Meng, Lin Shu, Jianing Zeng, Zhan Li, Kailin Lv, Haoyue Yang, Jie Hao:
MASL-AFU: A High Memory Access Efficiency 2-D Scalable LUT-Based Activation Function Unit for On-Device DNN Training. 707-719 - Yong-Tai Chen, Yen-Ting Chiu, Hao-Jiun Tu, Chao-Tsung Huang:
Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs. 720-732 - Eduardo Antonio Cesar da Costa, Morgana Macedo Azevedo da Rosa:
RCU- 2m: A VLSI Radix- 2m Cubic Unit. 733-745 - Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda:
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. 746-756 - Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, An Wang, Weijiang Wang, Hua Dang:
High-Performance Elliptic Curve Scalar Multiplication Architecture Based on Interleaved Mechanism. 757-770 - Mahipal Dargupally, Lomash Chandra Acharya, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. 771-779 - Donghyun Han, Sunghoon Kim, Dayoung Kim, Sungho Kang:
SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection. 780-792 - Mitchell Cooke, Nicola Nicolici:
An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion. 793-806 - Qian Chen, Xiaofeng Yang, Shengli Lu:
Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV. 807-820 - Pranav O. Mathews, Jennifer O. Hasler:
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems. 821-830 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features. 831-840 - Gustavo Aguirre, Freddy Forero, Víctor H. Champac, Michel Renovell, Florence Azaïs, Mariane Comte, Jean-Marc Gallière:
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. 841-852 - Hasan Al Shaikh, Shuvagata Saha, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification. 853-866 - Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang:
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing. 867-871 - Hui Hu, Bingbing Yao, Yi Shan, Lei Qiu:
A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs. 872-876 - Yongyuan Li, Xuhong Yin, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD). 877-881 - Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma:
A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. 882-886 - Jonghyun Oh, Kwanseo Park, Young-Ha Hwang:
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces. 887-891 - Yongyuan Li, Zhuliang Li, Wei Guo, Qiang Wu, Yongbo Zhang, Yong You, Zhangming Zhu:
A Combo EMI Suppression Scheme for Multimode PSR Flyback Converter. 892-896 - Yixiao Luo, Hongzhi Liang, Zeyu Peng, Yukui Yu, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs. 897-901 - Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao:
Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features". 902
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