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Journal of Low Power Electronics, Volume 10
Volume 10, Number 1, March 2014
- Assem A. M. Bsoul, Steven J. E. Wilton:
A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices. 1-15 - Francois Druilhe:
A Simplified Mathematical Toolbox for Thermal Runaway Analysis. 16-19 - K. Shyamala, V. Kamakoti:
ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization. 20-31 - Biswajit Patra, Amlan Chakrabarti
, Sanatan Chattopadhyay
Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes. 32-37 - Mohammad Hossein Hajkazemi, Amirali Baniasadi:
An Alternative Hybrid Power-Aware Adder for High-Performance Processors. 38-44 - Vijay Kumar Sharma, Manisha Pattanaik:
Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits. 45-52 - Umakanta Nanda
Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector. 53-57 - S. Raghavendran, B. Chitti Babu:
Performance Improvement of Soft Switching DC-DC Boost Converter for Photovoltaic (PV) Applications. 58-64 - Azhar Ul-Haq, Marium Jalal Chaudhry, Farhat Saleemi
Hybrid Fuel Cell Power System for Electric Vehicles Application. 65-71 - Dean Karolak, Thierry Taris, Yann Deval
Design of High Sensitivity Radiofrequency Energy Harvesters Dedicated to Low-Power Applications. 72-83 - Arun Kant Sharma, Shiva Asapu, Akshay Kumar Salimath
Read and Write Analysis for Balanced Pattern Memristor Crossbar Array. 84-87 - Bahniman Ghosh, Gaurav S. Solanki, Abhishek Banerjee:
Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy. 88-91 - Bahniman Ghosh, Punyasloka Bal, Partha Mondal, M. W. Akram:
Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize I on/I off by Drain Engineering and Work Function Engineering. 92-100 - Bahniman Ghosh, Neelam Surana, M. W. Akram, Ball Mukund Mani Tripathi:
In0 25Ga0 75As Channel Double Gate Junctionless Transistor. 101-106 - Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti:
XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. 107-115 - Nadine Azémard, Jörg Henkel:
Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013. 116-117 - Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville:
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. 118-126 - Omar Jonani Franco Piliado, Giancarlo Castaneda, Andre Juge, Gérard Ghibaudo
Characterization Methodology for MOSFET Local Systematic Variability in Presence of Statistical Variability. 127-136 - Mihai Tache, Valeriu Beiu
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates. 137-148 - Alexandre Fonseca, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod:
Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop. 149-162 - Letícia Maria Bolzani Poehls, Matteo Sonza Reorda
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013. 163-164 - Alexandre Boyer, Sonia Ben Dhia:
Effect of Aging on Power Integrity and Conducted Emission of Digital Integrated Circuits. 165-172 - Wenceslas Rahajandraibe
Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation. 173-181
Volume 10, Number 2, June 2014
- Yanqiu Huang
Accurate Energy-Aware Workload Distribution for Wireless Sensor Networks Using a Detailed Communication Energy Cost Model. 183-193 - Peng Ye, Youcong Ni, Xin Du, Datong Xie:
A Profile for GPS Data Reliable Transmission Based on Bluetooth Low Energy. 194-200 - Nasir Ali Kant
0.5V Sinh-Domain Design of Activation Functions and Neural Networks. 201-213 - Bahniman Ghosh, A. Ajay:
2-Bit Full Adder Implementation Using Single Spin Logic Paradigm. 214-219 - Arundhati Bhattacharya, Aminul Islam
Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET. 220-227 - Vasilis Kolios, Costas Psychalinos
Ultra-Low Voltage Realization of the Tau-Cell and Its Application for Filtering Electrocardiogram Signals. 228-235 - Saloni Varshney, Manish Goswami, B. R. Singh, Ashok Srivastava:
Low Power-Variable Resolution Analog-to-Digital Converter. 236-246 - M. Bhaskar
Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects. 247-258 - Shaahin Angizi
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata. 259-271 - Jangam Siva Chandra, Kandula Suresh, Bahniman Ghosh:
Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design. 272-278 - Cheolhwan Lim, Sunil Govardhan, Hyoungsoo Kim, Sungyong Jung, Kwangki Ryoo:
A CMOS Switched Capacitor Based Low Power Amperometric Readout Circuit for Microneedle Glucose Sensor. 279-285 - M. W. Akram, Bahniman Ghosh:
Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor. 286-292 - Bahniman Ghosh, Partha Mondal, M. W. Akram, Punyasloka Bal:
Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime. 293-296
Volume 10, Number 3, September 2014
- Jeffrey B. Goeders, Steven J. E. Wilton:
Power Aware Architecture Exploration for Field Programmable Gate Arrays. 297-312 - Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes
Spatially Distributed Dual-Spacer Null Convention Logic Design. 313-320 - Bahniman Ghosh, Abhinay Kumar:
Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks. 321-324 - Hasliza Hassan
Thermal Model with Metal Consideration for System-on-Chip Testing. 325-333 - Stéphane Burignat, Alexis De Vos:
Energy Consumption by Reversible ircuits in the 130 nm and 65 nm Nodes. 334-341 - Hao Liang, Yinshui Xia, Shiheng Wang, Libo Qian:
A Novel Low Power Three-Input OR/XNOR Gate Design. 342-346 - Hoang Vu Tran, Luc Cong Vu, Trung-Quan Nguyen, Thanh Tran, Huu-Thanh Nguyen
Sleep Mode and Wakeup Method for OpenFlow Switches. 347-353 - Bahniman Ghosh, Shibir Basak, Pranav Kumar Asthana:
Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate. 354-360 - Ankit Kumar Verma, Bahniman Ghosh, Bhaskar Awadhiya
Ab-Initio Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions. 361-364 - Bahniman Ghosh, Aayush Gupta:
Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering. 365-367 - Bahniman Ghosh, Aayush Gupta:
Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon. 368-372 - Filomila Kafe, Costas Psychalinos
0.5 V RMS-to-DC Converter Topologies Suitable for Implantable Biomedical Devices. 373-382 - Saheli Sarkhel
A Compact Two Dimensional Analytical Modeling of Nanoscale Fully Depleted Dual Material Gate Strained SOI/SON MOSFETs for Subdued SCEs. 383-391 - Prasanna Kumar Misra, S. Qureshi:
Impact of Collector Length on the Performance of NPN SiGe HBT on Thin Film SOI. 392-398 - Jimson Mathew, A. Prasad Vinod
Selected Articles from the IEEE ISED 2013 Conference. 399-400 - Mohamad Imran Bin Bandan
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System. 401-416 - Sumedh Dhabu, Kavallur Gopi Smitha
Design of Reconfigurable Filter Bank Architecture Using Improved Coefficient Decimation-Interpolation-Masking Technique for Multi-Standard Wireless Communication Receivers. 417-428 - Srinivas Sabbavarapu
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market. 429-442 - Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay:
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. 443-454 - Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan:
Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control. 455-466 - Luo Sun, Jimson Mathew, Samuel N. Pagliarini
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems. 467-478 - Manodipan Sahoo
On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications. 479-494 - Jos A. V. Prakash, Babita R. Jose:
A Low Cost Design of Time Division Multiplexing Based 3rd Order Continuous-Time Incremental ΣΔ Modulator with Excess Loop Delay. 495-505 - Sudip Roy, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty
An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications. 506-518 - Amit Acharyya
Energy-Efficient and High-Speed Robust System Design for Remote Cardiac Health Monitoring. 519-530
Volume 10, Number 4, December 2014
- Andrea Bartolini
Message Passing-Aware Power Management on Many-Core Systems. 531-549 - Yang Ge, Yukan Zhang, Qinru Qiu:
Distributed Task Migration in a Homogeneous Many-Core System for Leakage and Fan Power Reduction. 550-565 - Liang Men, Jia Di:
Asynchronous Parallel Platforms with Balanced Performance and Energy. 566-579 - Yuvaneet Bhaker, Princepreet Singh, Bahniman Ghosh:
Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device. 580-583 - Stéphane Burignat, Alexis De Vos:
A Technology Based Complexity Model for Reversible Cuccaro Ripple-Carry Adder. 584-592 - Venkatachalam Nithish Kumar
Low Power and Area Efficient Carry Select Adder. 593-601 - P. A. Gowri Sankar
Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes. 602-616 - Karthik Naishathrala Jayaraman, Vishwani D. Agrawal:
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. 617-628 - Shibir Basak, Bahniman Ghosh:
Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET. 629-634 - Cheolhwan Lim, Sujith S. Dermal, Sungyong Jung, Nosang Myung, Kwang-Ki Ryoo:
A Compact CMOS Electrochemical Sensor Readout Circuit for a Conductometric Sensor Array. 635-639
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