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William W. Walker
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2010 – 2019
- 2013
- [c14]Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada:
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC 2013: 28-29 - 2011
- [c13]Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker:
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC 2011: 346-348 - 2010
- [j12]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010)
2000 – 2009
- 2009
- [j11]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3580-3589 (2009) - [c12]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC 2009: 360-361 - 2008
- [j10]Marcus van Ierssel, Hisakatsu Yamaguchi, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker:
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(5): 1306-1315 (2008) - 2007
- [j9]Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A Leakage Current Replica Keeper for Dynamic Circuits. IEEE J. Solid State Circuits 42(1): 48-55 (2007) - [j8]Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker:
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. IEEE J. Solid State Circuits 42(10): 2224-2234 (2007) - [j7]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42(12): 2726-2735 (2007) - [c11]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC 2007: 224-598 - [c10]Vineet Wason, Rajeev Murgai, William W. Walker:
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design 2007: 271-277 - 2006
- [j6]Hisashige Ando, Akira Asato, Motoyuki Kawaba, Hideki Okawara, William W. Walker:
A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload. Inf. Media Technol. 1(1): 80-91 (2006) - [c9]Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura:
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. CICC 2006: 413-416 - [c8]Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study. ISQED 2006: 85-91 - [c7]Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker:
A 3.2Gb/s Semi-Blind-Oversampling CDR. ISSCC 2006: 1304-1313 - [c6]Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A leakage current replica keeper for dynamic circuits. ISSCC 2006: 1755-1764 - [c5]Nestoras Tzartzanis, William W. Walker:
A Reversible Poly-Phase Distributed VCO. ISSCC 2006: 2452-2461 - 2005
- [j5]Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda:
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits 40(4): 986-993 (2005) - [j4]Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005) - [j3]Nestoras Tzartzanis, William W. Walker:
Differential current-mode sensing for efficient on-chip global signaling. IEEE J. Solid State Circuits 40(11): 2141-2147 (2005) - [j2]Hisashige Ando, Nestoras Tzartzanis, William W. Walker:
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 865-868 (2005) - [c4]Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis. ICCAD 2005: 939-946 - 2004
- [j1]Nikola Nedovic, William W. Walker, Vojin G. Oklobdzija:
A test circuit for measurement of clocked storage element characteristics. IEEE J. Solid State Circuits 39(8): 1294-1304 (2004) - [c3]Makram M. Mansour, Amit Mehrotra, William W. Walker, Amit Narayan:
Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. ISCAS (5) 2004: 512-515 - 2003
- [c2]Nestoras Tzartzanis, William W. Walker:
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. ICCD 2003: 107- - [c1]Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker:
An efficient transistor optimizer for custom circuits. ISCAS (5) 2003: 197-200
Coauthor Index
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