default search action
CICC 2006: San Jose, California, USA
- Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. IEEE 2006, ISBN 1-4244-0075-9
- Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal
, Antonio J. López-Martín
Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs. 1-4 - Christopher M. Twigg, Paul E. Hasler:
A Large-Scale Reconfigurable Analog Signal Processor (RASP) IC. 5-8 - Arifur Rahman, Satyaki Das, Tim Tuan, Steven Trimberger:
Determination of Power Gating Granularity for FPGA Fabric. 9-12 - Rajit Manohar:
Reconfigurable Asynchronous Logic. 13-20 - Changhua Cao, Yanping Ding, Kenneth K. O:
A 50-GHz Phase-Locked Loop in 130-nm CMOS. 21-24 - Antonio Liscidini
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. 25-28 - William F. Andress, David S. Ricketts, Xiaofeng Li, Donhee Ham
Passive & Active Control of Regenerative Standing & Soliton Waves. 29-36 - Hui Zheng, Howard C. Luong
A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider. 37-40 - János Márkus, Philippe Deval, Vincent Quiquempoix, José B. Silva, Gabor C. Temes:
Incremental Delta-Sigma Structures for DC Measurement: an Overview. 41-48 - Zhiheng Cao, Tongyu Song, Shouli Yan:
A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers. 49-52 - Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto:
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. 53-56 - Tongyu Song, Zhiheng Cao, Shouli Yan:
A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter. 57-60 - Mona Safi-Harb, Gordon W. Roberts:
A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization. 61-64 - Mike Peng Li:
Jitter And Signaling Test For High-Speed Links. 65-72 - Shanthi Pavan, Tonse Laxminidhi:
A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters. 77-80 - Robert Bogdan Staszewski
Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS. 81-84 - Chunlei Shi, Brett C. Walker, Eric Zeisel, Brian Hu, Gene H. McAllister:
A Highly Integrated Power Management IC for Advanced Mobile Applications. 85-88 - Alireza Shirvani, Derek Cheung, Randy Tsang, Shafiq Jamal, Thomas Cho, Xiaodong Jin, Yonghua Song:
A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS. 89-92 - Massimo Bocchi, Mario de Dominicis, Claudio Mucci, Antonio Deledda, Fabio Campi, Andrea Lodi, Mario Toma, Roberto Guerrieri:
Design and implementation of a reconfigurable heterogeneous multiprocessor SoC. 93-96 - Rakesh H. Patel, William Bereza:
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. 97-100 - K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal:
Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC. 101-104 - Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. 105-108 - Sungdae Choi, Seong-Jun Song, Kyomin Sohn, Hyejung Kim, Joo-Young Kim, Namjun Cho, Jeong-Ho Woo, Jerald Yoo
A Multi-Nodes Human Body Communication Sensor Network Control Processor. 109-112 - David Su:
Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip. 113-120 - S. Beyer, R. Jaehne, W. Kluge, D. Eggert:
A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee. 121-124 - Albert C. Jerng, Charles G. Sodini:
A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter. 125-128 - Siray Akhtar, Mehmet Ipek, J. Lin, Robert Bogdan Staszewski
Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS. 129-132 - Luigi Panseri, Luca Romanò, Salvatore Levantino
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. 133-136 - Amin Shameli, Aminghasem Safarian, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis:
A Novel DAC Based Switching Power Amplifier for Polar Transmitter. 137-140 - Gang Liu, Tsu-Jae King Liu, Ali M. Niknejad:
A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement. 141-144 - Yong-Hee Lee, Moo-Yeol Choi, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim:
A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure. 145-148 - Erhan Ozalevli
Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors. 149-152 - Douglas A. Mercer:
Low Power Approaches to High Speed CMOS Current Steering DACs. 153-160 - Babak Nejati, Lawrence Larson:
An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC. 161-164 - Jing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer:
A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications. 165-168 - Patrick G. Drennan, M. L. Kniffin, D. R. Locascio:
Implications of Proximity Effects for Analog Design. 169-176 - Kenneth S. Kundert, Henry Chang:
Verification of Complex Analog Integrated Circuits. 177-184 - Saurabh K. Tiwary, Rob A. Rutenbar
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. 185-188 - Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula:
Predictive Modeling of the NBTI Effect for Reliable Design. 189-192 - Christoph Hagleitner, Anthony R. Bonaccio, Hugo E. Rothuizen, Dorothea Wiesmann, Jan Lienemann
Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage Device. 193-196 - Khaled Abdelfattah, Behzad Razavi:
Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators. 197-200 - Murali Shanmugasundaram, Shanthi Pavan:
Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. 201-204 - Mohammad Sharifkhani, Manoj Sachdev:
A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer. 205-208 - Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. 209-212 - Wonseok Oh, Bertan Bakkaloglu
A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier. 213-216 - Kamal El-Sankary, Mohamad Sawan:
10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC. 217-220 - Xiangtao Li, Wei-Min Lance Kuo, Yuan Lu, John D. Cressler:
A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT Technology. 221-224 - Xinyu Yu, Steven L. Garverick:
A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS. 225-228 - Sam Kavusi, Kunal Ghosh, Keith Fife, Abbas El Gamal:
A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays. 229-232 - Ashkan Olyaei, Roman Genov:
ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor. 233-236 - Thomas William Brown, Terri S. Fiez, Mikko Hakkarainen:
Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. 237-240 - Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour:
1.56 GHz On-chip Resonant Clocking in 130nm CMOS. 241-244 - Mohankumar N. Somasundaram, Dongsheng Ma:
Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation. 245-248 - Hong Yu, Rizwan Bashirullah:
A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics. 249-252 - Janghoon Song, Gilwon Yoon, Chulwoo Kim:
An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling. 253-256 - Sheng-Yu Peng, Muhammad Shakeel Qureshi, Arindam Basu
A Floating-gate Based Low-Power Capacitive Sensing Interface Circuit. 257-260 - Andrew W. Howard, Gu-Yeon Wei, William J. Dally, Paul Horowitz:
Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI. 261-264 - Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. 265-268 - Ye-Ming Li, Robert Wodnicki, Naveen Chandra, Naresh Rao:
An Integrated 90V Switch Array for Medical Ultrasound Applications. 269-272 - Kea-Tiong Tang, Rodney M. Goodman:
Towards a Wearable Electronic Nose Chip. 273-276 - Edward K. F. Lee, Eusebiu Matei, Anthony Lam, Taihu Li:
A 1V 420μW 32-channel Cortical Signal Interface. 277-280 - Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A 3D Multi-Aperture Image Sensor Architecture. 281-284 - Vladimir I. Prodanov, Mihai Banu:
GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling. 285-288 - Shahin Jafarabadi-Ashtiani
A Driving Scheme for AMOLED Displays Based on Current Feedback. 289-292 - Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. 293-296 - Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev:
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. 297-300 - Kostas Pagiamtzis
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. 301-304 - Liyang Pan, Dong Wu, Guangjun Yang, Lei Sun, Huiqing Pang, Jun Zhu:
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory. 305-308 - Luca Ciccarelli, Domenico Loparco, Massimiliano Innocenti, Andrea Lodi, Claudio Mucci, Pier Luigi Rolandi:
A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs. 309-312 - Giby Samson
A 0.13 μm Low-power Race-free Programmable Logic Array. 313-316 - Liping Guo, Mackenzie R. Scott, Rajeevan Amirtharajah
An Energy Scalable Computational Array for Sensor Signal Processing. 317-320 - Sizhong Chen, Fei Sun, Tong Zhang:
Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency. 321-324 - Hao Zhong, Tong Zhang, Erich F. Haratsch:
VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel. 325-328 - Shoushun Chen, Amine Bermak
A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor. 329-332 - George Suárez Martínez, Manuel Jiménez-Cedeño:
Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators. 333-336 - Jie Gu, John Keane, Sachin S. Sapatnekar
Width Quantization Aware FinFET Circuit Design. 337-340 - Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. 341-344 - Vishal Bhargava, N. Haider, N. Sarpotdar:
IO Clock Network Skew & Performance Analysis: A Pentium-D Case Study. 345-348 - Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury:
Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked Dividers. 349-352 - Chun-Jung Chen, Tai-Ning Yang, Jenn-Dong Sun:
The Backward-traversing Relaxation Algorithm for Circuit Simulation. 353-356 - Patrick P. Mercier
Yield and Cost Modeling for 3D Chip Stack Technologies. 357-360 - Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih:
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs. 361-364 - Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren:
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement. 365-368 - Mizuki Motoyoshi, Minoru Fujishima
In Situ Evaluation Method for On-Chip Inductors Using Oscillator Response. 369-372 - Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi:
A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. 373-376 - Ja-Yol Lee, Kwi-Dong Kim, Jong-Kee Kwon, Seung-Chul Lee, Jongdae Kim, Sang-Heung Lee:
A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications. 377-380 - Harish Krishnaswamy, Hossein Hashemi:
Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study. 381-384 - Karan S. Bhatia, Sami Hyvonen, Elyse Rosenbaum:
An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications. 385-388 - Bagher Afshar, Ali M. Niknejad:
X/Ku Band CMOS LNA Design Techniques. 389-392 - Sayf Alalusi, Robert W. Brodersen:
A 60GHz Phased Array in CMOS. 393-396 - Chihun Lee, Lan-chou Cho, Shen-Iuan Liu:
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. 397-400 - David A. Yokoyama-Martin, Kannan Krishna, John T. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, James Parker, Ross Segelken, Jeff L. Sonntag, K. Umino, J. Upton, Daniel Weinlader, Skye Wolfer:
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. 401-404 - Kin-Joe Sham, Mahmoud Reza Ahmadi, S. B. Gerry Talbot, Ramesh Harjani:
FEXT Crosstalk Cancellation for High-Speed Serial Link Design. 405-408 - Jongshin Shin, Ilwon Seo, Jiyoung Kim, Seung-Hee Yang, Chiwon Kim, Jaehyun Park, Hyungoo Kim, Myoungbo Kwak, GhyBoong Hong:
A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA. 409-412 - Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura:
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. 413-416 - Amber Han-Yuan Tan, Gu-Yeon Wei:
Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator. 417-420 - Yasushi Yamagata, Hiroki Shirai, Hirotoshi Sugimura, S. Arai, Tomoko Wake, Ken Inoue, Takashi Sakoh, Masato Sakao, Takaho Tanigawa:
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor. 421-427 - Kazutami Arimoto, Fukashi Morishita
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. 429-432 - Saakshi Gangwal, Saibal Mukhopadhyay, Kaushik Roy:
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM. 433-436 - Eishi Ibe, S. S. Chung, ShiJie Wen, Hironaru Yamaguchi, Yasuo Yahagi, Hideaki Kameyama, Shigehisa Yamamoto, Takashi Akioka:
Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling. 437-444 - Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin:
Low Cost Test of High Bandwidth Embedded Memories. 445-448 - Joe Walsh, G. Scott:
High-Temperature, High Reliability EEPROM Design For Automotive Applications. 449-452 - Igor Arsovski, Reid Wistort:
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories. 453-456 - Arijit Raychowdhury, Jeong-Il Kim, Dimitrios Peroulis
Integrated MEMS Switches for Leakage Control of Battery Operated Systems. 457-460 - Jae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang
CNT based mechanical devices for ULSI memory. 461-464 - Levent Yobas, Hongmiao Ji, Wing-Cheong Hui, Yu Chen, Tit Meng Lim, Chew-Kiat Heng
Nucleic Acid Extraction, Amplification, and Detection on Si-based Microfluidic Platforms. 465-472 - Kenneth K. O, Kihong Kim, Brian A. Floyd
Silicon Integrated Circuits Incorporating Antennas. 473-480 - Ashutosh Verma, Behzad Razavi:
Frequency-Based Measurement of Mismatches Between Small Capacitors. 481-484 - Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Kyoung-Ho Moon, Jae-Whui Kim:
A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors. 485-488 - Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn:
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. 489-492 - Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. 493-496 - Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon:
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. 497-500 - Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. 501-504 - Shoji Kawahito:
Low-Power Design of Pipeline A/D Converters. 505-512 - Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC. 513-516 - Robert Bogdan Staszewski
Digital Signal Processing for RF at 45-nm CMOS and Beyond. 517-522 - Dayu Yang, Weining Ni, Fa Foster Dai, Yin Shi, Richard C. Jaeger:
Delta-Sigma Modulation in Direct Digital Frequency Synthesis. 523-526 - Jonne Lindeberg, Olli Väänänen, Jussi Pirkkalaniemi, Marko Kosunen, Kari Halonen:
OFDM modulator with digital IF and on-chip D/A-converter. 527-530 - Ralph Etienne-Cummings, Swati Mehta, Ralf M. Philipp, Viktor Gruev:
Neuromorphic Vision Systems for Mobile Applications. 531-534 - Byeong-Gyu Nam
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems. 535-538 - Charles Thomas, Matthew Cooke, Oliver Ridler, Koen van den Beld, Dominic Yip, Uwe Sontowski, Adriel Kind, Gongyu Zhou, Yi-Chen Li, Long Ung, Rami Banna, Benjamin Widdup, Thomas Prokop, Mark Bickerstaff, Graeme Woodward
A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile Terminals. 539-542 - E. Matu, Hendrik Seidel, Torsten Limberg, Pablo Robelly, Gerhard P. Fettweis:
A GFLOPS Vector-DSP for Broadband Wireless Applications. 543-546 - Saibal Mukhopadhyay, Amit Agarwal, Qikai Chen, Kaushik Roy:
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design. 547-554 - Ana Sonia Leon, Brian Langley, Jinuk Luke Shin:
The UltraSPARC T1 Processor: CMT Reliability. 555-562 - Takashi Sato
A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop. 563-566 - Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, Frank Woytowich, Bob Bassett:
Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs. 567-570 - Yin-Lung Ryan Lu, Yung-Huei Lee, William J. Mcmahon, Tze-Ching Fung:
Robust Inductor Design for RF Circuits. 571-574 - Kohei Onizuka, Hiroshi Kawaguchi
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. 575-578 - Ivan Koudar:
Balanced Low Noise High Dynamic Photodiode Interface for Automotive. 579-582 - Lasse Aaltonen, Mikko Saukoski, Kari Halonen:
On-chip Digitally Tunable High Voltage Generator for Electrostatic Control of Micromechanical Devices. 583-586 - Arifur Rahman, John Trezza, Bernard J. New, Stephen Trimberger:
Die Stacking Technology for Terabit Chip-to-Chip Communications. 587-590 - Jan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta
Wireline Equalization using Pulse-Width Modulation. 591-598 - Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu:
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. 599-602 - Pavan Kumar Hanumolu, Min-Gyu Kim, Gu-Yeon Wei, Un-Ku Moon:
A 1.6Gbps Digital Clock and Data Recovery Circuit. 603-606 - Keith E. Sanborn, Dongsheng Ma, Vadim V. Ivanov:
A Sub-i V Low-Noise Bandgap Voltage Reference. 607-610 - Srinivasan Venkatesh, Guillermo J. Serrano
A Compact Programmable CMOS Reference With ±40μV Accuracy. 611-614 - Mohammad A. Al-Shyoukh, Raul A. Perez, Hoi Lee:
A Transient-Enhanced 20μA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation. 615-618 - Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai:
Compact outside-rail circuit structure by single-cascode two-transistor topology. 619-622 - J. Watts:
Enhancing Productivity by Continuously Improving Standard Compact Models. 623-630 - Cynthia L. Recker, Brandt Braswell, Patrick G. Drennan, Colin C. McAndrew:
A Web Tool for Interactive Exploration of Analog Design Tradeoffs. 631-634 - Bhavna Agrawal, Frank Liu, Sani R. Nassif:
Circuit Optimization Using Scale Based Sensitivities. 635-638 - Wolfganh Horn, Martin Gräfling, Günter Gross, Manfred Steiner, Josef Treiber, Rory Dickman, Kuno Reis:
A 4-Channel High-Precision Constant Current Control ASIC for Automotive Transmission Applications. 639-642 - Hong-Wei Huang, Hsin-Hsin Ho, Chieh-Ching Chien, Ke-Horng Chen
Ditherng Skip Modulator with a Width Controller for Ultra-wide-load High-Efficiency DC-DC Converters. 643-646 - Sang-Min Lee, Hyunsik Park, Bruce A. Wooley:
Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array. 647-650 - Chul Bum Kim, Byung Hyuk Kim, Yong Soo Lee, Han Jung, Hee Chul Lee:
Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays. 651-654 - Ajit Sharma, Faisal Zaman, Farrokh Ayazi:
A 104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork Microgyroscopes. 655-658 - Amir M. Sodagar, Khalil Najafi, Kensall D. Wise, Maysam Ghovanloo:
Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical Microsystems. 659-662 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors. 663-670
- Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. 671-674 - Behzad Razavi:
Mutual Injection Pulling Between Oscillators. 675-678 - Stefaan Decoutere, Piet Wambacq, Vaidy Subramanian, Jonathan Borremans, Abdelkarim Mercha:
Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges. 679-686 - Ying-Kuang Chen, Yves Baeyens, Nils Weimann, Jaesik Lee, Joe Weiner, Vincent Houtsma, Yang Yang:
Recent Advances in III-V Electronics. 687-690 - Fu-Liang Yang
Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices. 691-694 - James S. Dunn, David L. Harame, Alvin J. Joseph, Stephen A. St. Onge, Natalie B. Feilchenfeld, Louis D. Lanzerotti, Bradley A. Orner, Ephrem G. Gebreselasie, Jeffrey B. Johnson, Douglas D. Coolbaugh, Rick Rassel, Marwan Khater:
SiGe BiCMOS Trends - Today and Tomorrow. 695-702 - R. Mahajan, D. Mallik, Robert Sankman, K. Radhakrishnan, C. Chiu, J. He:
Advances and Challenges in Flip-Chip Packaging. 703-709 - Andries J. Scholten
Compact modeling of noise in CMOS. 711-716 - Volker Blaschke, James Victory:
A Scalable Model Methodology for Octagonal Differential and Single-Ended Inductors. 717-720 - Yasuhiro Ogasahara
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects. 721-724 - Akira Tanabe, Ken'ichiro Hijioka, Yoshihiro Hayashi
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model. 725-728 - Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram:
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. 729-732 - Behzad Mesgarzadeh, Atila Alvandpour:
First-Harmonic Injection-Locked Ring Oscillators. 733-736 - Ahmad Mirzaei, Mohammad E. Heidari, Asad A. Abidi:
Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation. 737-740 - Ting Mei, Jaijeet S. Roychowdhury:
Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators. 741-744 - Tae-Young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong-Chan Lim, Kuk-Tae Hong:
A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery. 745-748 - Amber Han-Yuan Tan, Gu-Yeon Wei:
Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance. 749-752 - JunYoung Park, Michael P. Flynn:
A Low Jitter Multi-Phase PLL with Capacitive Coupling. 753-756 - Prabir C. Maulik, Douglas A. Mercer:
A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS. 757-760 - Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. 761-764 - Ahmet Tekin
Integrated VCO Design for MICS Transceivers. 765-768 - Raymond E. Barnett, Jin Liu:
A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID. 769-772 - Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. 773-776 - Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou:
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. 777-780 - Ruilin Wang, Cheng-Kok Koh, Byunghoo Jung, William J. Chappell:
Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration. 781-784 - Lin Zhang, Berkehan Ciftcioglu, Michael C. Huang
Injection-Locked Clocking: A New GHz Clock Distribution Scheme. 785-788 - Robert Bogdan Staszewski
Digital RF Processor Techniques for Single-Chip Radios. 789-796 - Nuntachai Poobuapheun, Wei-Hung Chen, Zdravko Boos, Ali M. Niknejad:
A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers. 797-800 - Shuzuo Lou, Hui Zheng, Howard C. Luong
A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System. 801-804 - Aminghasem Safarian, Lei Zhou, Payam Heydari:
A Distributed RF Front-End for UWB Receivers. 805-808 - (Withdrawn) A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC. 809-812
- Gökçe Keskin, Xin Li, Lawrence T. Pileggi:
Active On-Die Suppression of Power Supply Noise. 813-816 - Mohamed Bouhamame, Jean-Robert Tourret, Luca Lo Coco, Serge Toutain, Olivier Pasquier:
A Fully Integrated DC/DC Converter for Tunable RF Filters. 817-820 - Poki Chen, Chun-Chi Chen, Tuo-Kuang Chen, Shi-Wei Chen:
A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming. 821-824 - Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan:
A Unity-Gain Buffer with Reduced Offset and Gain Error. 825-828 - Masum Hossain, Anthony Chan Carusone
A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS. 829-832 - Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
A 0.6V Highly Linear Switched-R-MOSFET-C Filter. 833-836 - Koutani Kagoshima, Shuichi Kawama, Shinji Toyoyama, Kunihiko Iizuka:
Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration. 837-840 - Krishnakumar Sundaresan, Gavin K. Ho, Siavash Pourkamali, Farrokh Ayazi:
A Low Phase Noise 100MHz Silicon BAW Reference Oscillator. 841-844 - Jamil Kawa, Charles C. Chiang, Raul Camposano:
EDA Challenges in Nano-scale Technology. 845-851 - Ning Lu:
Statistical and Corner Modeling of Interconnect Resistance and Capacitance. 853-856 - Gerhard Rappitsch, Oliver Eisenberger, Bernd Obermeier, Andreas Ripp, Michael Pronath:
Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells. 857-860 - Yasuhiro Ogasahara
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. 861-864 - Mitsuya Fukazawa, Makoto Nagata
Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform. 865-868 - Jinsook Kim, Weiping Ni, Edwin C. Kan:
Crosstalk Reduction with Nonlinear Transmission Lines for High-Speed VLSI System. 869-872
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-04 20:30 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: